1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/rockchip,rv1106-cru.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: ROCKCHIP rv1106 Family Clock Control Module Binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Elaine Zhang <zhangqing@rock-chips.com> 11*4882a593Smuzhiyun - Heiko Stuebner <heiko@sntech.de> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun The RV1106 clock controller generates the clock and also implements a 15*4882a593Smuzhiyun reset controller for SoC peripherals. 16*4882a593Smuzhiyun (examples: provide SCLK_UART2\PCLK_UART2 and SRST_P_UART2\SRST_S_UART2 for UART module) 17*4882a593Smuzhiyun Each clock is assigned an identifier and client nodes can use this identifier 18*4882a593Smuzhiyun to specify the clock which they consume. All available clocks are defined as 19*4882a593Smuzhiyun preprocessor macros in the dt-bindings/clock/rv1106-cru.h headers and can be 20*4882a593Smuzhiyun used in device tree sources. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunproperties: 23*4882a593Smuzhiyun compatible: 24*4882a593Smuzhiyun enum: 25*4882a593Smuzhiyun - rockchip,rv1106-cru 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun "#clock-cells": 31*4882a593Smuzhiyun const: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun "#reset-cells": 34*4882a593Smuzhiyun const: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clocks: true 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun assigned-clocks: 39*4882a593Smuzhiyun minItems: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun assigned-clock-parents: 42*4882a593Smuzhiyun minItems: 1 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun assigned-clock-rates: 45*4882a593Smuzhiyun minItems: 1 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunrequired: 48*4882a593Smuzhiyun - compatible 49*4882a593Smuzhiyun - reg 50*4882a593Smuzhiyun - "#clock-cells" 51*4882a593Smuzhiyun - "#reset-cells" 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunadditionalProperties: false 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunexamples: 56*4882a593Smuzhiyun # Clock Control Module node: 57*4882a593Smuzhiyun - | 58*4882a593Smuzhiyun cru: clock-controller@ff3a0000 { 59*4882a593Smuzhiyun compatible = "rockchip,rv1106-cru"; 60*4882a593Smuzhiyun reg = <0xff3a0000 0x20000>; 61*4882a593Smuzhiyun #clock-cells = <1>; 62*4882a593Smuzhiyun #reset-cells = <1>; 63*4882a593Smuzhiyun }; 64