1*4882a593SmuzhiyunRockchip RK618 Clock and Reset Unit 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding: 4*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties : 7*4882a593Smuzhiyun- compatible : Should be "rockchip,rk618-cru" 8*4882a593Smuzhiyun- clocks : Should contain phandle and clock specifiers for the input clock: 9*4882a593Smuzhiyun the AP I2S master clock output(mclk) "clkin", and the AP LCDC master 10*4882a593Smuzhiyun dclk output(dclk) "lcdc0_dclkp". 11*4882a593Smuzhiyun- #clock-cells : Should be 1. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample: 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun&rk618 { 16*4882a593Smuzhiyun CRU: cru { 17*4882a593Smuzhiyun compatible = "rockchip,rk618-cru"; 18*4882a593Smuzhiyun clocks = <&cru SCLK_I2S_8CH_OUT>, <&cru DCLK_VOP>; 19*4882a593Smuzhiyun clock-names = "clkin", "lcdc0_dclkp"; 20*4882a593Smuzhiyun assigned-clocks = <&CRU SCALER_PLLIN_CLK>, <&CRU VIF_PLLIN_CLK>, 21*4882a593Smuzhiyun <&CRU HDMI_CLK>, <&CRU SCALER_CLK>, 22*4882a593Smuzhiyun <&CRU CODEC_CLK>; 23*4882a593Smuzhiyun assigned-clock-parents = <&CRU LCDC0_CLK>, <&CRU LCDC0_CLK>, 24*4882a593Smuzhiyun <&CRU VIF0_CLK>, <&CRU SCALER_PLL_CLK>, 25*4882a593Smuzhiyun <&cru SCLK_I2S_8CH_OUT>; 26*4882a593Smuzhiyun #clock-cells = <1>; 27*4882a593Smuzhiyun status = "okay"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30