xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* Renesas R9A06G032 SYSCTRL
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired Properties:
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun  - compatible: Must be:
6*4882a593Smuzhiyun    - "renesas,r9a06g032-sysctrl"
7*4882a593Smuzhiyun  - reg: Base address and length of the SYSCTRL IO block.
8*4882a593Smuzhiyun  - #clock-cells: Must be 1
9*4882a593Smuzhiyun  - clocks: References to the parent clocks:
10*4882a593Smuzhiyun	- external 40mhz crystal.
11*4882a593Smuzhiyun	- external (optional) 32.768khz
12*4882a593Smuzhiyun	- external (optional) jtag input
13*4882a593Smuzhiyun	- external (optional) RGMII_REFCLK
14*4882a593Smuzhiyun  - clock-names: Must be:
15*4882a593Smuzhiyun        clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
16*4882a593Smuzhiyun  - #power-domain-cells: Must be 0
17*4882a593Smuzhiyun
18*4882a593SmuzhiyunExamples
19*4882a593Smuzhiyun--------
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun  - SYSCTRL node:
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	sysctrl: system-controller@4000c000 {
24*4882a593Smuzhiyun		compatible = "renesas,r9a06g032-sysctrl";
25*4882a593Smuzhiyun		reg = <0x4000c000 0x1000>;
26*4882a593Smuzhiyun		#clock-cells = <1>;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		clocks = <&ext_mclk>, <&ext_rtc_clk>,
29*4882a593Smuzhiyun				<&ext_jtag_clk>, <&ext_rgmii_ref>;
30*4882a593Smuzhiyun		clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
31*4882a593Smuzhiyun		#power-domain-cells = <0>;
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun  - Other nodes can use the clocks provided by SYSCTRL as in:
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	#include <dt-bindings/clock/r9a06g032-sysctrl.h>
37*4882a593Smuzhiyun	uart0: serial@40060000 {
38*4882a593Smuzhiyun		compatible = "snps,dw-apb-uart";
39*4882a593Smuzhiyun		reg = <0x40060000 0x400>;
40*4882a593Smuzhiyun		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
41*4882a593Smuzhiyun		reg-shift = <2>;
42*4882a593Smuzhiyun		reg-io-width = <4>;
43*4882a593Smuzhiyun		clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
44*4882a593Smuzhiyun		clock-names = "baudclk", "apb_pclk";
45*4882a593Smuzhiyun		power-domains = <&sysctrl>;
46*4882a593Smuzhiyun	};
47