1*4882a593Smuzhiyun* Renesas H8/300 divider clock 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired Properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun - compatible: Must be "renesas,h8300-div-clock" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun - clocks: Reference to the parent clocks ("extal1" and "extal2") 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun - #clock-cells: Must be 1 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - reg: Base address and length of the divide rate selector 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun - renesas,width: bit width of selector 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample 16*4882a593Smuzhiyun------- 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun cclk: cclk { 19*4882a593Smuzhiyun compatible = "renesas,h8300-div-clock"; 20*4882a593Smuzhiyun clocks = <&xclk>; 21*4882a593Smuzhiyun #clock-cells = <0>; 22*4882a593Smuzhiyun reg = <0xfee01b 2>; 23*4882a593Smuzhiyun renesas,width = <2>; 24*4882a593Smuzhiyun }; 25