1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Geert Uytterhoeven <geert+renesas@glider.be> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are 14*4882a593Smuzhiyun organized in groups of up to 32 gates. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun This device tree binding describes a single 32 gate clocks group per node. 17*4882a593Smuzhiyun Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle 18*4882a593Smuzhiyun and the clock index in the group, from 0 to 31. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun items: 23*4882a593Smuzhiyun - enum: 24*4882a593Smuzhiyun - renesas,r7s72100-mstp-clocks # RZ/A1 25*4882a593Smuzhiyun - renesas,r8a73a4-mstp-clocks # R-Mobile APE6 26*4882a593Smuzhiyun - renesas,r8a7740-mstp-clocks # R-Mobile A1 27*4882a593Smuzhiyun - renesas,r8a7778-mstp-clocks # R-Car M1 28*4882a593Smuzhiyun - renesas,r8a7779-mstp-clocks # R-Car H1 29*4882a593Smuzhiyun - renesas,sh73a0-mstp-clocks # SH-Mobile AG5 30*4882a593Smuzhiyun - const: renesas,cpg-mstp-clocks 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun reg: 33*4882a593Smuzhiyun minItems: 1 34*4882a593Smuzhiyun items: 35*4882a593Smuzhiyun - description: Module Stop Control Register (MSTPCR) 36*4882a593Smuzhiyun - description: Module Stop Status Register (MSTPSR) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clocks: 39*4882a593Smuzhiyun minItems: 1 40*4882a593Smuzhiyun maxItems: 32 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun '#clock-cells': 43*4882a593Smuzhiyun const: 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun clock-indices: 46*4882a593Smuzhiyun minItems: 1 47*4882a593Smuzhiyun maxItems: 32 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun clock-output-names: 50*4882a593Smuzhiyun minItems: 1 51*4882a593Smuzhiyun maxItems: 32 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunrequired: 54*4882a593Smuzhiyun - compatible 55*4882a593Smuzhiyun - reg 56*4882a593Smuzhiyun - clocks 57*4882a593Smuzhiyun - '#clock-cells' 58*4882a593Smuzhiyun - clock-indices 59*4882a593Smuzhiyun - clock-output-names 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunadditionalProperties: false 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunexamples: 64*4882a593Smuzhiyun - | 65*4882a593Smuzhiyun #include <dt-bindings/clock/r8a73a4-clock.h> 66*4882a593Smuzhiyun mstp2_clks: mstp2_clks@e6150138 { 67*4882a593Smuzhiyun compatible = "renesas,r8a73a4-mstp-clocks", 68*4882a593Smuzhiyun "renesas,cpg-mstp-clocks"; 69*4882a593Smuzhiyun reg = <0xe6150138 4>, <0xe6150040 4>; 70*4882a593Smuzhiyun clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 71*4882a593Smuzhiyun <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 72*4882a593Smuzhiyun #clock-cells = <1>; 73*4882a593Smuzhiyun clock-indices = < 74*4882a593Smuzhiyun R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 75*4882a593Smuzhiyun R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 76*4882a593Smuzhiyun R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 77*4882a593Smuzhiyun R8A73A4_CLK_DMAC 78*4882a593Smuzhiyun >; 79*4882a593Smuzhiyun clock-output-names = 80*4882a593Smuzhiyun "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3", 81*4882a593Smuzhiyun "dmac"; 82*4882a593Smuzhiyun }; 83