xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Renesas CPG DIV6 Clock
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Geert Uytterhoeven <geert+renesas@glider.be>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription:
13*4882a593Smuzhiyun  The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
14*4882a593Smuzhiyun  Generator (CPG). Their clock input is divided by a configurable factor from 1
15*4882a593Smuzhiyun  to 64.
16*4882a593Smuzhiyun
17*4882a593Smuzhiyunproperties:
18*4882a593Smuzhiyun  compatible:
19*4882a593Smuzhiyun    items:
20*4882a593Smuzhiyun      - enum:
21*4882a593Smuzhiyun          - renesas,r8a73a4-div6-clock # R-Mobile APE6
22*4882a593Smuzhiyun          - renesas,r8a7740-div6-clock # R-Mobile A1
23*4882a593Smuzhiyun          - renesas,sh73a0-div6-clock  # SH-Mobile AG5
24*4882a593Smuzhiyun      - const: renesas,cpg-div6-clock
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  reg:
27*4882a593Smuzhiyun    maxItems: 1
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  clocks:
30*4882a593Smuzhiyun    oneOf:
31*4882a593Smuzhiyun      - maxItems: 1
32*4882a593Smuzhiyun      - maxItems: 4
33*4882a593Smuzhiyun      - maxItems: 8
34*4882a593Smuzhiyun    description:
35*4882a593Smuzhiyun      For clocks with multiple parents, invalid settings must be specified as
36*4882a593Smuzhiyun      "<0>".
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun  '#clock-cells':
39*4882a593Smuzhiyun    const: 0
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun  clock-output-names: true
42*4882a593Smuzhiyun
43*4882a593Smuzhiyunrequired:
44*4882a593Smuzhiyun  - compatible
45*4882a593Smuzhiyun  - reg
46*4882a593Smuzhiyun  - clocks
47*4882a593Smuzhiyun  - '#clock-cells'
48*4882a593Smuzhiyun
49*4882a593SmuzhiyunadditionalProperties: false
50*4882a593Smuzhiyun
51*4882a593Smuzhiyunexamples:
52*4882a593Smuzhiyun  - |
53*4882a593Smuzhiyun    #include <dt-bindings/clock/r8a73a4-clock.h>
54*4882a593Smuzhiyun    sdhi2_clk: sdhi2_clk@e615007c {
55*4882a593Smuzhiyun            compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
56*4882a593Smuzhiyun            reg = <0xe615007c 4>;
57*4882a593Smuzhiyun            clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
58*4882a593Smuzhiyun                     <&extal2_clk>;
59*4882a593Smuzhiyun            #clock-cells = <0>;
60*4882a593Smuzhiyun    };
61