1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Taniya Das <tdas@codeaurora.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun Qualcomm graphics clock control module which supports the clocks, resets and 14*4882a593Smuzhiyun power domains on MSM8998. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun See also dt-bindings/clock/qcom,gpucc-msm8998.h. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunproperties: 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun const: qcom,msm8998-gpucc 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun clocks: 23*4882a593Smuzhiyun items: 24*4882a593Smuzhiyun - description: Board XO source 25*4882a593Smuzhiyun - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun clock-names: 28*4882a593Smuzhiyun items: 29*4882a593Smuzhiyun - const: xo 30*4882a593Smuzhiyun - const: gpll0 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun '#clock-cells': 33*4882a593Smuzhiyun const: 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun '#reset-cells': 36*4882a593Smuzhiyun const: 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun '#power-domain-cells': 39*4882a593Smuzhiyun const: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun reg: 42*4882a593Smuzhiyun maxItems: 1 43*4882a593Smuzhiyun 44*4882a593Smuzhiyunrequired: 45*4882a593Smuzhiyun - compatible 46*4882a593Smuzhiyun - reg 47*4882a593Smuzhiyun - clocks 48*4882a593Smuzhiyun - clock-names 49*4882a593Smuzhiyun - '#clock-cells' 50*4882a593Smuzhiyun - '#reset-cells' 51*4882a593Smuzhiyun - '#power-domain-cells' 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunadditionalProperties: false 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunexamples: 56*4882a593Smuzhiyun - | 57*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,gcc-msm8998.h> 58*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,rpmcc.h> 59*4882a593Smuzhiyun clock-controller@5065000 { 60*4882a593Smuzhiyun compatible = "qcom,msm8998-gpucc"; 61*4882a593Smuzhiyun #clock-cells = <1>; 62*4882a593Smuzhiyun #reset-cells = <1>; 63*4882a593Smuzhiyun #power-domain-cells = <1>; 64*4882a593Smuzhiyun reg = <0x05065000 0x9000>; 65*4882a593Smuzhiyun clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0_OUT_MAIN>; 66*4882a593Smuzhiyun clock-names = "xo", "gpll0"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun... 69