1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Global Clock & Reset Controller Binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Stephen Boyd <sboyd@kernel.org> 11*4882a593Smuzhiyun - Taniya Das <tdas@codeaurora.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun Qualcomm global clock control module which supports the clocks, resets and 15*4882a593Smuzhiyun power domains. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun See also: 18*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-apq8084.h 19*4882a593Smuzhiyun - dt-bindings/reset/qcom,gcc-apq8084.h 20*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-ipq4019.h 21*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-ipq6018.h 22*4882a593Smuzhiyun - dt-bindings/reset/qcom,gcc-ipq6018.h 23*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) 24*4882a593Smuzhiyun - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) 25*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-msm8939.h 26*4882a593Smuzhiyun - dt-bindings/reset/qcom,gcc-msm8939.h 27*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-msm8660.h 28*4882a593Smuzhiyun - dt-bindings/reset/qcom,gcc-msm8660.h 29*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-msm8974.h 30*4882a593Smuzhiyun - dt-bindings/reset/qcom,gcc-msm8974.h 31*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-msm8994.h 32*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-mdm9615.h 33*4882a593Smuzhiyun - dt-bindings/reset/qcom,gcc-mdm9615.h 34*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660) 35*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-sdm845.h 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunproperties: 38*4882a593Smuzhiyun compatible: 39*4882a593Smuzhiyun enum: 40*4882a593Smuzhiyun - qcom,gcc-apq8084 41*4882a593Smuzhiyun - qcom,gcc-ipq4019 42*4882a593Smuzhiyun - qcom,gcc-ipq6018 43*4882a593Smuzhiyun - qcom,gcc-ipq8064 44*4882a593Smuzhiyun - qcom,gcc-msm8660 45*4882a593Smuzhiyun - qcom,gcc-msm8916 46*4882a593Smuzhiyun - qcom,gcc-msm8939 47*4882a593Smuzhiyun - qcom,gcc-msm8960 48*4882a593Smuzhiyun - qcom,gcc-msm8974 49*4882a593Smuzhiyun - qcom,gcc-msm8974pro 50*4882a593Smuzhiyun - qcom,gcc-msm8974pro-ac 51*4882a593Smuzhiyun - qcom,gcc-msm8994 52*4882a593Smuzhiyun - qcom,gcc-mdm9615 53*4882a593Smuzhiyun - qcom,gcc-sdm630 54*4882a593Smuzhiyun - qcom,gcc-sdm660 55*4882a593Smuzhiyun - qcom,gcc-sdm845 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun '#clock-cells': 58*4882a593Smuzhiyun const: 1 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun '#reset-cells': 61*4882a593Smuzhiyun const: 1 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun '#power-domain-cells': 64*4882a593Smuzhiyun const: 1 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun reg: 67*4882a593Smuzhiyun maxItems: 1 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun protected-clocks: 70*4882a593Smuzhiyun description: 71*4882a593Smuzhiyun Protected clock specifier list as per common clock binding. 72*4882a593Smuzhiyun 73*4882a593Smuzhiyunrequired: 74*4882a593Smuzhiyun - compatible 75*4882a593Smuzhiyun - reg 76*4882a593Smuzhiyun - '#clock-cells' 77*4882a593Smuzhiyun - '#reset-cells' 78*4882a593Smuzhiyun - '#power-domain-cells' 79*4882a593Smuzhiyun 80*4882a593SmuzhiyunadditionalProperties: false 81*4882a593Smuzhiyun 82*4882a593Smuzhiyunexamples: 83*4882a593Smuzhiyun # Example for GCC for MSM8960: 84*4882a593Smuzhiyun - | 85*4882a593Smuzhiyun clock-controller@900000 { 86*4882a593Smuzhiyun compatible = "qcom,gcc-msm8960"; 87*4882a593Smuzhiyun reg = <0x900000 0x4000>; 88*4882a593Smuzhiyun #clock-cells = <1>; 89*4882a593Smuzhiyun #reset-cells = <1>; 90*4882a593Smuzhiyun #power-domain-cells = <1>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun... 93