1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Display Clock & Reset Controller Binding for SC7180 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Taniya Das <tdas@codeaurora.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun Qualcomm display clock control module which supports the clocks, resets and 14*4882a593Smuzhiyun power domains on SC7180. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun See also dt-bindings/clock/qcom,dispcc-sc7180.h. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunproperties: 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun const: qcom,sc7180-dispcc 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun clocks: 23*4882a593Smuzhiyun items: 24*4882a593Smuzhiyun - description: Board XO source 25*4882a593Smuzhiyun - description: GPLL0 source from GCC 26*4882a593Smuzhiyun - description: Byte clock from DSI PHY 27*4882a593Smuzhiyun - description: Pixel clock from DSI PHY 28*4882a593Smuzhiyun - description: Link clock from DP PHY 29*4882a593Smuzhiyun - description: VCO DIV clock from DP PHY 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun clock-names: 32*4882a593Smuzhiyun items: 33*4882a593Smuzhiyun - const: bi_tcxo 34*4882a593Smuzhiyun - const: gcc_disp_gpll0_clk_src 35*4882a593Smuzhiyun - const: dsi0_phy_pll_out_byteclk 36*4882a593Smuzhiyun - const: dsi0_phy_pll_out_dsiclk 37*4882a593Smuzhiyun - const: dp_phy_pll_link_clk 38*4882a593Smuzhiyun - const: dp_phy_pll_vco_div_clk 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun '#clock-cells': 41*4882a593Smuzhiyun const: 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun '#reset-cells': 44*4882a593Smuzhiyun const: 1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun '#power-domain-cells': 47*4882a593Smuzhiyun const: 1 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun reg: 50*4882a593Smuzhiyun maxItems: 1 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunrequired: 53*4882a593Smuzhiyun - compatible 54*4882a593Smuzhiyun - reg 55*4882a593Smuzhiyun - clocks 56*4882a593Smuzhiyun - clock-names 57*4882a593Smuzhiyun - '#clock-cells' 58*4882a593Smuzhiyun - '#reset-cells' 59*4882a593Smuzhiyun - '#power-domain-cells' 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunadditionalProperties: false 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunexamples: 64*4882a593Smuzhiyun - | 65*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,gcc-sc7180.h> 66*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,rpmh.h> 67*4882a593Smuzhiyun clock-controller@af00000 { 68*4882a593Smuzhiyun compatible = "qcom,sc7180-dispcc"; 69*4882a593Smuzhiyun reg = <0x0af00000 0x200000>; 70*4882a593Smuzhiyun clocks = <&rpmhcc RPMH_CXO_CLK>, 71*4882a593Smuzhiyun <&gcc GCC_DISP_GPLL0_CLK_SRC>, 72*4882a593Smuzhiyun <&dsi_phy 0>, 73*4882a593Smuzhiyun <&dsi_phy 1>, 74*4882a593Smuzhiyun <&dp_phy 0>, 75*4882a593Smuzhiyun <&dp_phy 1>; 76*4882a593Smuzhiyun clock-names = "bi_tcxo", 77*4882a593Smuzhiyun "gcc_disp_gpll0_clk_src", 78*4882a593Smuzhiyun "dsi0_phy_pll_out_byteclk", 79*4882a593Smuzhiyun "dsi0_phy_pll_out_dsiclk", 80*4882a593Smuzhiyun "dp_phy_pll_link_clk", 81*4882a593Smuzhiyun "dp_phy_pll_vco_div_clk"; 82*4882a593Smuzhiyun #clock-cells = <1>; 83*4882a593Smuzhiyun #reset-cells = <1>; 84*4882a593Smuzhiyun #power-domain-cells = <1>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun... 87