1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/qcom,msm8996-apcc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm clock controller for MSM8996 CPUs 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Loic Poulain <loic.poulain@linaro.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster 14*4882a593Smuzhiyun and clock 1 is for Perf cluster. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun enum: 19*4882a593Smuzhiyun - qcom,msm8996-apcc 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun reg: 22*4882a593Smuzhiyun maxItems: 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun '#clock-cells': 25*4882a593Smuzhiyun const: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun clocks: 28*4882a593Smuzhiyun items: 29*4882a593Smuzhiyun - description: Primary PLL clock for power cluster (little) 30*4882a593Smuzhiyun - description: Primary PLL clock for perf cluster (big) 31*4882a593Smuzhiyun - description: Alternate PLL clock for power cluster (little) 32*4882a593Smuzhiyun - description: Alternate PLL clock for perf cluster (big) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun clock-names: 35*4882a593Smuzhiyun items: 36*4882a593Smuzhiyun - const: pwrcl_pll 37*4882a593Smuzhiyun - const: perfcl_pll 38*4882a593Smuzhiyun - const: pwrcl_alt_pll 39*4882a593Smuzhiyun - const: perfcl_alt_pll 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunrequired: 42*4882a593Smuzhiyun - compatible 43*4882a593Smuzhiyun - reg 44*4882a593Smuzhiyun - '#clock-cells' 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunadditionalProperties: false 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunexamples: 49*4882a593Smuzhiyun - | 50*4882a593Smuzhiyun kryocc: clock-controller@6400000 { 51*4882a593Smuzhiyun compatible = "qcom,msm8996-apcc"; 52*4882a593Smuzhiyun reg = <0x6400000 0x90000>; 53*4882a593Smuzhiyun #clock-cells = <1>; 54*4882a593Smuzhiyun }; 55