1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Multimedia Clock & Reset Controller Binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Jeffrey Hugo <jhugo@codeaurora.org> 11*4882a593Smuzhiyun - Taniya Das <tdas@codeaurora.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun Qualcomm multimedia clock control module which supports the clocks, resets and 15*4882a593Smuzhiyun power domains. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun enum: 20*4882a593Smuzhiyun - qcom,mmcc-apq8064 21*4882a593Smuzhiyun - qcom,mmcc-apq8084 22*4882a593Smuzhiyun - qcom,mmcc-msm8660 23*4882a593Smuzhiyun - qcom,mmcc-msm8960 24*4882a593Smuzhiyun - qcom,mmcc-msm8974 25*4882a593Smuzhiyun - qcom,mmcc-msm8996 26*4882a593Smuzhiyun - qcom,mmcc-msm8998 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun clocks: 29*4882a593Smuzhiyun items: 30*4882a593Smuzhiyun - description: Board XO source 31*4882a593Smuzhiyun - description: Board sleep source 32*4882a593Smuzhiyun - description: Global PLL 0 clock 33*4882a593Smuzhiyun - description: DSI phy instance 0 dsi clock 34*4882a593Smuzhiyun - description: DSI phy instance 0 byte clock 35*4882a593Smuzhiyun - description: DSI phy instance 1 dsi clock 36*4882a593Smuzhiyun - description: DSI phy instance 1 byte clock 37*4882a593Smuzhiyun - description: HDMI phy PLL clock 38*4882a593Smuzhiyun - description: DisplayPort phy PLL vco clock 39*4882a593Smuzhiyun - description: DisplayPort phy PLL link clock 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun clock-names: 42*4882a593Smuzhiyun items: 43*4882a593Smuzhiyun - const: xo 44*4882a593Smuzhiyun - const: sleep 45*4882a593Smuzhiyun - const: gpll0 46*4882a593Smuzhiyun - const: dsi0dsi 47*4882a593Smuzhiyun - const: dsi0byte 48*4882a593Smuzhiyun - const: dsi1dsi 49*4882a593Smuzhiyun - const: dsi1byte 50*4882a593Smuzhiyun - const: hdmipll 51*4882a593Smuzhiyun - const: dpvco 52*4882a593Smuzhiyun - const: dplink 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun '#clock-cells': 55*4882a593Smuzhiyun const: 1 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun '#reset-cells': 58*4882a593Smuzhiyun const: 1 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun '#power-domain-cells': 61*4882a593Smuzhiyun const: 1 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun reg: 64*4882a593Smuzhiyun maxItems: 1 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun protected-clocks: 67*4882a593Smuzhiyun description: 68*4882a593Smuzhiyun Protected clock specifier list as per common clock binding 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun vdd-gfx-supply: 71*4882a593Smuzhiyun description: 72*4882a593Smuzhiyun Regulator supply for the GPU_GX GDSC 73*4882a593Smuzhiyun 74*4882a593Smuzhiyunrequired: 75*4882a593Smuzhiyun - compatible 76*4882a593Smuzhiyun - reg 77*4882a593Smuzhiyun - '#clock-cells' 78*4882a593Smuzhiyun - '#reset-cells' 79*4882a593Smuzhiyun - '#power-domain-cells' 80*4882a593Smuzhiyun 81*4882a593SmuzhiyunadditionalProperties: false 82*4882a593Smuzhiyun 83*4882a593Smuzhiyunif: 84*4882a593Smuzhiyun properties: 85*4882a593Smuzhiyun compatible: 86*4882a593Smuzhiyun contains: 87*4882a593Smuzhiyun const: qcom,mmcc-msm8998 88*4882a593Smuzhiyun 89*4882a593Smuzhiyunthen: 90*4882a593Smuzhiyun required: 91*4882a593Smuzhiyun - clocks 92*4882a593Smuzhiyun - clock-names 93*4882a593Smuzhiyun 94*4882a593Smuzhiyunexamples: 95*4882a593Smuzhiyun # Example for MMCC for MSM8960: 96*4882a593Smuzhiyun - | 97*4882a593Smuzhiyun clock-controller@4000000 { 98*4882a593Smuzhiyun compatible = "qcom,mmcc-msm8960"; 99*4882a593Smuzhiyun reg = <0x4000000 0x1000>; 100*4882a593Smuzhiyun #clock-cells = <1>; 101*4882a593Smuzhiyun #reset-cells = <1>; 102*4882a593Smuzhiyun #power-domain-cells = <1>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun... 105