1*4882a593SmuzhiyunQualcomm LPASS Clock Controller Binding 2*4882a593Smuzhiyun----------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties : 5*4882a593Smuzhiyun- compatible : shall contain "qcom,sdm845-lpasscc" 6*4882a593Smuzhiyun- #clock-cells : from common clock binding, shall contain 1. 7*4882a593Smuzhiyun- reg : shall contain base register address and size, 8*4882a593Smuzhiyun in the order 9*4882a593Smuzhiyun Index-0 maps to LPASS_CC register region 10*4882a593Smuzhiyun Index-1 maps to LPASS_QDSP6SS register region 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOptional properties : 13*4882a593Smuzhiyun- reg-names : register names of LPASS domain 14*4882a593Smuzhiyun "cc", "qdsp6ss". 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunThe below node has to be defined in the cases where the LPASS peripheral loader 19*4882a593Smuzhiyunwould bring the subsystem out of reset. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun lpasscc: clock-controller@17014000 { 22*4882a593Smuzhiyun compatible = "qcom,sdm845-lpasscc"; 23*4882a593Smuzhiyun reg = <0x17014000 0x1f004>, <0x17300000 0x200>; 24*4882a593Smuzhiyun reg-names = "cc", "qdsp6ss"; 25*4882a593Smuzhiyun #clock-cells = <1>; 26*4882a593Smuzhiyun }; 27