1*4882a593SmuzhiyunQualcomm LPASS Clock & Reset Controller Binding 2*4882a593Smuzhiyun------------------------------------------------ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties : 5*4882a593Smuzhiyun- compatible : shall contain only one of the following: 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun "qcom,lcc-msm8960" 8*4882a593Smuzhiyun "qcom,lcc-apq8064" 9*4882a593Smuzhiyun "qcom,lcc-ipq8064" 10*4882a593Smuzhiyun "qcom,lcc-mdm9615" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- reg : shall contain base register location and length 13*4882a593Smuzhiyun- #clock-cells : shall contain 1 14*4882a593Smuzhiyun- #reset-cells : shall contain 1 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun clock-controller@28000000 { 18*4882a593Smuzhiyun compatible = "qcom,lcc-ipq8064"; 19*4882a593Smuzhiyun reg = <0x28000000 0x1000>; 20*4882a593Smuzhiyun #clock-cells = <1>; 21*4882a593Smuzhiyun #reset-cells = <1>; 22*4882a593Smuzhiyun }; 23