1*4882a593SmuzhiyunHigh-Frequency PLL (HFPLL) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunPROPERTIES 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: 6*4882a593Smuzhiyun Usage: required 7*4882a593Smuzhiyun Value type: <string>: 8*4882a593Smuzhiyun shall contain only one of the following. The generic 9*4882a593Smuzhiyun compatible "qcom,hfpll" should be also included. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun "qcom,hfpll-ipq8064", "qcom,hfpll" 12*4882a593Smuzhiyun "qcom,hfpll-apq8064", "qcom,hfpll" 13*4882a593Smuzhiyun "qcom,hfpll-msm8974", "qcom,hfpll" 14*4882a593Smuzhiyun "qcom,hfpll-msm8960", "qcom,hfpll" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- reg: 17*4882a593Smuzhiyun Usage: required 18*4882a593Smuzhiyun Value type: <prop-encoded-array> 19*4882a593Smuzhiyun Definition: address and size of HPLL registers. An optional second 20*4882a593Smuzhiyun element specifies the address and size of the alias 21*4882a593Smuzhiyun register region. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- clocks: 24*4882a593Smuzhiyun Usage: required 25*4882a593Smuzhiyun Value type: <prop-encoded-array> 26*4882a593Smuzhiyun Definition: reference to the xo clock. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun- clock-names: 29*4882a593Smuzhiyun Usage: required 30*4882a593Smuzhiyun Value type: <stringlist> 31*4882a593Smuzhiyun Definition: must be "xo". 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun- clock-output-names: 34*4882a593Smuzhiyun Usage: required 35*4882a593Smuzhiyun Value type: <string> 36*4882a593Smuzhiyun Definition: Name of the PLL. Typically hfpllX where X is a CPU number 37*4882a593Smuzhiyun starting at 0. Otherwise hfpll_Y where Y is more specific 38*4882a593Smuzhiyun such as "l2". 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun1) An HFPLL for the L2 cache. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun clock-controller@f9016000 { 45*4882a593Smuzhiyun compatible = "qcom,hfpll-ipq8064", "qcom,hfpll"; 46*4882a593Smuzhiyun reg = <0xf9016000 0x30>; 47*4882a593Smuzhiyun clocks = <&xo_board>; 48*4882a593Smuzhiyun clock-names = "xo"; 49*4882a593Smuzhiyun clock-output-names = "hfpll_l2"; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun2) An HFPLL for CPU0. This HFPLL has the alias register region. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun clock-controller@f908a000 { 55*4882a593Smuzhiyun compatible = "qcom,hfpll-ipq8064", "qcom,hfpll"; 56*4882a593Smuzhiyun reg = <0xf908a000 0x30>, <0xf900a000 0x30>; 57*4882a593Smuzhiyun clocks = <&xo_board>; 58*4882a593Smuzhiyun clock-names = "xo"; 59*4882a593Smuzhiyun clock-output-names = "hfpll0"; 60*4882a593Smuzhiyun }; 61