1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Global Clock & Reset Controller Binding for MSM8998 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Stephen Boyd <sboyd@kernel.org> 11*4882a593Smuzhiyun - Taniya Das <tdas@codeaurora.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun Qualcomm global clock control module which supports the clocks, resets and 15*4882a593Smuzhiyun power domains on MSM8998. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun See also: 18*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-msm8998.h 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun const: qcom,gcc-msm8998 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun clocks: 25*4882a593Smuzhiyun items: 26*4882a593Smuzhiyun - description: Board XO source 27*4882a593Smuzhiyun - description: Sleep clock source 28*4882a593Smuzhiyun - description: USB 3.0 phy pipe clock 29*4882a593Smuzhiyun - description: UFS phy rx symbol clock for pipe 0 30*4882a593Smuzhiyun - description: UFS phy rx symbol clock for pipe 1 31*4882a593Smuzhiyun - description: UFS phy tx symbol clock 32*4882a593Smuzhiyun - description: PCIE phy pipe clock 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun clock-names: 35*4882a593Smuzhiyun items: 36*4882a593Smuzhiyun - const: xo 37*4882a593Smuzhiyun - const: sleep_clk 38*4882a593Smuzhiyun - const: usb3_pipe 39*4882a593Smuzhiyun - const: ufs_rx_symbol0 40*4882a593Smuzhiyun - const: ufs_rx_symbol1 41*4882a593Smuzhiyun - const: ufs_tx_symbol0 42*4882a593Smuzhiyun - const: pcie0_pipe 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun '#clock-cells': 45*4882a593Smuzhiyun const: 1 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun '#reset-cells': 48*4882a593Smuzhiyun const: 1 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun '#power-domain-cells': 51*4882a593Smuzhiyun const: 1 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun reg: 54*4882a593Smuzhiyun maxItems: 1 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun protected-clocks: 57*4882a593Smuzhiyun description: 58*4882a593Smuzhiyun Protected clock specifier list as per common clock binding. 59*4882a593Smuzhiyun 60*4882a593Smuzhiyunrequired: 61*4882a593Smuzhiyun - compatible 62*4882a593Smuzhiyun - clocks 63*4882a593Smuzhiyun - clock-names 64*4882a593Smuzhiyun - reg 65*4882a593Smuzhiyun - '#clock-cells' 66*4882a593Smuzhiyun - '#reset-cells' 67*4882a593Smuzhiyun - '#power-domain-cells' 68*4882a593Smuzhiyun 69*4882a593SmuzhiyunadditionalProperties: false 70*4882a593Smuzhiyun 71*4882a593Smuzhiyunexamples: 72*4882a593Smuzhiyun - | 73*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,rpmcc.h> 74*4882a593Smuzhiyun clock-controller@100000 { 75*4882a593Smuzhiyun compatible = "qcom,gcc-msm8998"; 76*4882a593Smuzhiyun #clock-cells = <1>; 77*4882a593Smuzhiyun #reset-cells = <1>; 78*4882a593Smuzhiyun #power-domain-cells = <1>; 79*4882a593Smuzhiyun reg = <0x00100000 0xb0000>; 80*4882a593Smuzhiyun clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 81*4882a593Smuzhiyun <&sleep>, 82*4882a593Smuzhiyun <0>, 83*4882a593Smuzhiyun <0>, 84*4882a593Smuzhiyun <0>, 85*4882a593Smuzhiyun <0>, 86*4882a593Smuzhiyun <0>; 87*4882a593Smuzhiyun clock-names = "xo", 88*4882a593Smuzhiyun "sleep_clk", 89*4882a593Smuzhiyun "usb3_pipe", 90*4882a593Smuzhiyun "ufs_rx_symbol0", 91*4882a593Smuzhiyun "ufs_rx_symbol1", 92*4882a593Smuzhiyun "ufs_tx_symbol0", 93*4882a593Smuzhiyun "pcie0_pipe"; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun... 96