1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Global Clock & Reset Controller Bindingfor IPQ8074 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Stephen Boyd <sboyd@kernel.org> 11*4882a593Smuzhiyun - Taniya Das <tdas@codeaurora.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun Qualcomm global clock control module which supports the clocks, resets and 15*4882a593Smuzhiyun power domains on IPQ8074. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun See also: 18*4882a593Smuzhiyun - dt-bindings/clock/qcom,gcc-ipq8074.h 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun const: qcom,gcc-ipq8074 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun '#clock-cells': 25*4882a593Smuzhiyun const: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun '#reset-cells': 28*4882a593Smuzhiyun const: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun reg: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun protected-clocks: 34*4882a593Smuzhiyun description: 35*4882a593Smuzhiyun Protected clock specifier list as per common clock binding. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunrequired: 38*4882a593Smuzhiyun - compatible 39*4882a593Smuzhiyun - reg 40*4882a593Smuzhiyun - '#clock-cells' 41*4882a593Smuzhiyun - '#reset-cells' 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunadditionalProperties: false 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunexamples: 46*4882a593Smuzhiyun - | 47*4882a593Smuzhiyun clock-controller@1800000 { 48*4882a593Smuzhiyun compatible = "qcom,gcc-ipq8074"; 49*4882a593Smuzhiyun reg = <0x01800000 0x80000>; 50*4882a593Smuzhiyun #clock-cells = <1>; 51*4882a593Smuzhiyun #reset-cells = <1>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun... 54