1*4882a593SmuzhiyunBinding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired Properties: 6*4882a593Smuzhiyun- compatible: has to be "qca,<soctype>-pll" and one of the following 7*4882a593Smuzhiyun fallbacks: 8*4882a593Smuzhiyun - "qca,ar7100-pll" 9*4882a593Smuzhiyun - "qca,ar7240-pll" 10*4882a593Smuzhiyun - "qca,ar9130-pll" 11*4882a593Smuzhiyun - "qca,ar9330-pll" 12*4882a593Smuzhiyun - "qca,ar9340-pll" 13*4882a593Smuzhiyun - "qca,qca9550-pll" 14*4882a593Smuzhiyun- reg: Base address and size of the controllers memory area 15*4882a593Smuzhiyun- clock-names: Name of the input clock, has to be "ref" 16*4882a593Smuzhiyun- clocks: phandle of the external reference clock 17*4882a593Smuzhiyun- #clock-cells: has to be one 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional properties: 20*4882a593Smuzhiyun- clock-output-names: should be "cpu", "ddr", "ahb" 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun pll-controller@18050000 { 25*4882a593Smuzhiyun compatible = "qca,ar9132-pll", "qca,ar9130-pll"; 26*4882a593Smuzhiyun reg = <0x18050000 0x20>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun clock-names = "ref"; 29*4882a593Smuzhiyun clocks = <&extosc>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #clock-cells = <1>; 32*4882a593Smuzhiyun clock-output-names = "cpu", "ddr", "ahb"; 33*4882a593Smuzhiyun }; 34