1*4882a593SmuzhiyunNVIDIA Tegra30 Clock And Reset Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding: 4*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe CAR (Clock And Reset) Controller on Tegra is the HW module responsible 7*4882a593Smuzhiyunfor muxing and gating Tegra's clocks, and setting their rates. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties : 10*4882a593Smuzhiyun- compatible : Should be "nvidia,tegra30-car" 11*4882a593Smuzhiyun- reg : Should contain CAR registers location and length 12*4882a593Smuzhiyun- clocks : Should contain phandle and clock specifiers for two clocks: 13*4882a593Smuzhiyun the 32 KHz "32k_in", and the board-specific oscillator "osc". 14*4882a593Smuzhiyun- #clock-cells : Should be 1. 15*4882a593Smuzhiyun In clock consumers, this cell represents the clock ID exposed by the 16*4882a593Smuzhiyun CAR. The assignments may be found in header file 17*4882a593Smuzhiyun <dt-bindings/clock/tegra30-car.h>. 18*4882a593Smuzhiyun- #reset-cells : Should be 1. 19*4882a593Smuzhiyun In clock consumers, this cell represents the bit number in the CAR's 20*4882a593Smuzhiyun array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample SoC include file: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun/ { 25*4882a593Smuzhiyun tegra_car: clock { 26*4882a593Smuzhiyun compatible = "nvidia,tegra30-car"; 27*4882a593Smuzhiyun reg = <0x60006000 0x1000>; 28*4882a593Smuzhiyun #clock-cells = <1>; 29*4882a593Smuzhiyun #reset-cells = <1>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun usb@c5004000 { 33*4882a593Smuzhiyun clocks = <&tegra_car TEGRA30_CLK_USB2>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunExample board file: 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun/ { 40*4882a593Smuzhiyun clocks { 41*4882a593Smuzhiyun compatible = "simple-bus"; 42*4882a593Smuzhiyun #address-cells = <1>; 43*4882a593Smuzhiyun #size-cells = <0>; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun osc: clock@0 { 46*4882a593Smuzhiyun compatible = "fixed-clock"; 47*4882a593Smuzhiyun reg = <0>; 48*4882a593Smuzhiyun #clock-cells = <0>; 49*4882a593Smuzhiyun clock-frequency = <12000000>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun clk_32k: clock@1 { 53*4882a593Smuzhiyun compatible = "fixed-clock"; 54*4882a593Smuzhiyun reg = <1>; 55*4882a593Smuzhiyun #clock-cells = <0>; 56*4882a593Smuzhiyun clock-frequency = <32768>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun &tegra_car { 61*4882a593Smuzhiyun clocks = <&clk_32k> <&osc>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun}; 64