1*4882a593Smuzhiyun* Nuvoton NPCM7XX Clock Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunNuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which 4*4882a593Smuzhiyungenerates and supplies clocks to all modules within the BMC. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunExternal clocks: 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunThere are six fixed clocks that are generated outside the BMC. All clocks are of 9*4882a593Smuzhiyuna known fixed value that cannot be changed. clk_refclk, clk_mcbypck and 10*4882a593Smuzhiyunclk_sysbypck are inputs to the clock controller. 11*4882a593Smuzhiyunclk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the 12*4882a593Smuzhiyunnetwork. They are set on the device tree, but not used by the clock module. The 13*4882a593Smuzhiyunnetwork devices use them directly. 14*4882a593SmuzhiyunExample can be found below. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunAll available clocks are defined as preprocessor macros in: 17*4882a593Smuzhiyundt-bindings/clock/nuvoton,npcm7xx-clock.h 18*4882a593Smuzhiyunand can be reused as DT sources. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunRequired Properties of clock controller: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton 23*4882a593Smuzhiyun Poleg BMC NPCM750 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun - reg: physical base address of the clock controller and length of 26*4882a593Smuzhiyun memory mapped region. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun - #clock-cells: should be 1. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExample: Clock controller node: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clk: clock-controller@f0801000 { 33*4882a593Smuzhiyun compatible = "nuvoton,npcm750-clk"; 34*4882a593Smuzhiyun #clock-cells = <1>; 35*4882a593Smuzhiyun reg = <0xf0801000 0x1000>; 36*4882a593Smuzhiyun clock-names = "refclk", "sysbypck", "mcbypck"; 37*4882a593Smuzhiyun clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: Required external clocks for network: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* external reference clock */ 43*4882a593Smuzhiyun clk_refclk: clk-refclk { 44*4882a593Smuzhiyun compatible = "fixed-clock"; 45*4882a593Smuzhiyun #clock-cells = <0>; 46*4882a593Smuzhiyun clock-frequency = <25000000>; 47*4882a593Smuzhiyun clock-output-names = "refclk"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* external reference clock for cpu. float in normal operation */ 51*4882a593Smuzhiyun clk_sysbypck: clk-sysbypck { 52*4882a593Smuzhiyun compatible = "fixed-clock"; 53*4882a593Smuzhiyun #clock-cells = <0>; 54*4882a593Smuzhiyun clock-frequency = <800000000>; 55*4882a593Smuzhiyun clock-output-names = "sysbypck"; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* external reference clock for MC. float in normal operation */ 59*4882a593Smuzhiyun clk_mcbypck: clk-mcbypck { 60*4882a593Smuzhiyun compatible = "fixed-clock"; 61*4882a593Smuzhiyun #clock-cells = <0>; 62*4882a593Smuzhiyun clock-frequency = <800000000>; 63*4882a593Smuzhiyun clock-output-names = "mcbypck"; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* external clock signal rg1refck, supplied by the phy */ 67*4882a593Smuzhiyun clk_rg1refck: clk-rg1refck { 68*4882a593Smuzhiyun compatible = "fixed-clock"; 69*4882a593Smuzhiyun #clock-cells = <0>; 70*4882a593Smuzhiyun clock-frequency = <125000000>; 71*4882a593Smuzhiyun clock-output-names = "clk_rg1refck"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* external clock signal rg2refck, supplied by the phy */ 75*4882a593Smuzhiyun clk_rg2refck: clk-rg2refck { 76*4882a593Smuzhiyun compatible = "fixed-clock"; 77*4882a593Smuzhiyun #clock-cells = <0>; 78*4882a593Smuzhiyun clock-frequency = <125000000>; 79*4882a593Smuzhiyun clock-output-names = "clk_rg2refck"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun clk_xin: clk-xin { 83*4882a593Smuzhiyun compatible = "fixed-clock"; 84*4882a593Smuzhiyun #clock-cells = <0>; 85*4882a593Smuzhiyun clock-frequency = <50000000>; 86*4882a593Smuzhiyun clock-output-names = "clk_xin"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun 90*4882a593SmuzhiyunExample: GMAC controller node that consumes two clocks: a generated clk by the 91*4882a593Smuzhiyunclock controller and a fixed clock from DT (clk_rg1refck). 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun ethernet0: ethernet@f0802000 { 94*4882a593Smuzhiyun compatible = "snps,dwmac"; 95*4882a593Smuzhiyun reg = <0xf0802000 0x2000>; 96*4882a593Smuzhiyun interrupts = <0 14 4>; 97*4882a593Smuzhiyun interrupt-names = "macirq"; 98*4882a593Smuzhiyun clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; 99*4882a593Smuzhiyun clock-names = "stmmaceth", "clk_gmac"; 100*4882a593Smuzhiyun }; 101