1*4882a593SmuzhiyunDevice Tree Clock bindings for cpu clock of Marvell EBU platforms 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : shall be one of the following: 5*4882a593Smuzhiyun "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP 6*4882a593Smuzhiyun "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC 7*4882a593Smuzhiyun- reg : Address and length of the clock complex register set, followed 8*4882a593Smuzhiyun by address and length of the PMU DFS registers 9*4882a593Smuzhiyun- #clock-cells : should be set to 1. 10*4882a593Smuzhiyun- clocks : shall be the input parent clock phandle for the clock. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyuncpuclk: clock-complex@d0018700 { 13*4882a593Smuzhiyun #clock-cells = <1>; 14*4882a593Smuzhiyun compatible = "marvell,armada-xp-cpu-clock"; 15*4882a593Smuzhiyun reg = <0xd0018700 0xA0>, <0x1c054 0x10>; 16*4882a593Smuzhiyun clocks = <&coreclk 1>; 17*4882a593Smuzhiyun} 18*4882a593Smuzhiyun 19*4882a593Smuzhiyuncpu@0 { 20*4882a593Smuzhiyun compatible = "marvell,sheeva-v7"; 21*4882a593Smuzhiyun reg = <0>; 22*4882a593Smuzhiyun clocks = <&cpuclk 0>; 23*4882a593Smuzhiyun}; 24