1*4882a593SmuzhiyunDevice Tree Clock bindings for arch-moxart 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunMOXA ART SoCs allow to determine PLL output and APB frequencies 8*4882a593Smuzhiyunby reading registers holding multiplier and divisor information. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunPLL: 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunRequired properties: 14*4882a593Smuzhiyun- compatible : Must be "moxa,moxart-pll-clock" 15*4882a593Smuzhiyun- #clock-cells : Should be 0 16*4882a593Smuzhiyun- reg : Should contain registers location and length 17*4882a593Smuzhiyun- clocks : Should contain phandle + clock-specifier for the parent clock 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional properties: 20*4882a593Smuzhiyun- clock-output-names : Should contain clock name 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunAPB: 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunRequired properties: 26*4882a593Smuzhiyun- compatible : Must be "moxa,moxart-apb-clock" 27*4882a593Smuzhiyun- #clock-cells : Should be 0 28*4882a593Smuzhiyun- reg : Should contain registers location and length 29*4882a593Smuzhiyun- clocks : Should contain phandle + clock-specifier for the parent clock 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunOptional properties: 32*4882a593Smuzhiyun- clock-output-names : Should contain clock name 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunFor example: 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun clk_pll: clk_pll@98100000 { 38*4882a593Smuzhiyun compatible = "moxa,moxart-pll-clock"; 39*4882a593Smuzhiyun #clock-cells = <0>; 40*4882a593Smuzhiyun reg = <0x98100000 0x34>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun clk_apb: clk_apb@98100000 { 44*4882a593Smuzhiyun compatible = "moxa,moxart-apb-clock"; 45*4882a593Smuzhiyun #clock-cells = <0>; 46*4882a593Smuzhiyun reg = <0x98100000 0x34>; 47*4882a593Smuzhiyun clocks = <&clk_pll>; 48*4882a593Smuzhiyun }; 49