1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/milbeaut-clock.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Milbeaut SoCs Clock Controller Binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Taichi Sugaya <sugaya.taichi@socionext.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun Milbeaut SoCs Clock controller is an integrated clock controller, which 14*4882a593Smuzhiyun generates and supplies to all modules. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun This binding uses common clock bindings 17*4882a593Smuzhiyun [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunproperties: 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun oneOf: 22*4882a593Smuzhiyun - items: 23*4882a593Smuzhiyun - enum: 24*4882a593Smuzhiyun - socionext,milbeaut-m10v-ccu 25*4882a593Smuzhiyun clocks: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun description: external clock 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun '#clock-cells': 30*4882a593Smuzhiyun const: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunrequired: 33*4882a593Smuzhiyun - compatible 34*4882a593Smuzhiyun - reg 35*4882a593Smuzhiyun - clocks 36*4882a593Smuzhiyun - '#clock-cells' 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunadditionalProperties: false 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunexamples: 41*4882a593Smuzhiyun # Clock controller node: 42*4882a593Smuzhiyun - | 43*4882a593Smuzhiyun m10v-clk-ctrl@1d021000 { 44*4882a593Smuzhiyun compatible = "socionext,milbeaut-m10v-clk-ccu"; 45*4882a593Smuzhiyun reg = <0x1d021000 0x4000>; 46*4882a593Smuzhiyun #clock-cells = <1>; 47*4882a593Smuzhiyun clocks = <&clki40mhz>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun # Required an external clock for Clock controller node: 51*4882a593Smuzhiyun - | 52*4882a593Smuzhiyun clocks { 53*4882a593Smuzhiyun clki40mhz: clki40mhz { 54*4882a593Smuzhiyun compatible = "fixed-clock"; 55*4882a593Smuzhiyun #clock-cells = <0>; 56*4882a593Smuzhiyun clock-frequency = <40000000>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun /* other clocks */ 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun # The clock consumer shall specify the desired clock-output of the clock 62*4882a593Smuzhiyun # controller as below by specifying output-id in its "clk" phandle cell. 63*4882a593Smuzhiyun # 2: uart 64*4882a593Smuzhiyun # 4: 32-bit timer 65*4882a593Smuzhiyun # 7: UHS-I/II 66*4882a593Smuzhiyun - | 67*4882a593Smuzhiyun serial@1e700010 { 68*4882a593Smuzhiyun compatible = "socionext,milbeaut-usio-uart"; 69*4882a593Smuzhiyun reg = <0x1e700010 0x10>; 70*4882a593Smuzhiyun interrupts = <0 141 0x4>, <0 149 0x4>; 71*4882a593Smuzhiyun interrupt-names = "rx", "tx"; 72*4882a593Smuzhiyun clocks = <&clk 2>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun... 76