1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Microchip Sparx5 DPLL Clock 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Lars Povlsen <lars.povlsen@microchip.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The Sparx5 DPLL clock controller generates and supplies clock to 14*4882a593Smuzhiyun various peripherals within the SoC. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: microchip,sparx5-dpll 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun clocks: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun '#clock-cells': 27*4882a593Smuzhiyun const: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunrequired: 30*4882a593Smuzhiyun - compatible 31*4882a593Smuzhiyun - reg 32*4882a593Smuzhiyun - clocks 33*4882a593Smuzhiyun - '#clock-cells' 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunadditionalProperties: false 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunexamples: 38*4882a593Smuzhiyun # Clock provider for eMMC: 39*4882a593Smuzhiyun - | 40*4882a593Smuzhiyun lcpll_clk: lcpll-clk { 41*4882a593Smuzhiyun compatible = "fixed-clock"; 42*4882a593Smuzhiyun #clock-cells = <0>; 43*4882a593Smuzhiyun clock-frequency = <2500000000>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun clks: clock-controller@61110000c { 46*4882a593Smuzhiyun compatible = "microchip,sparx5-dpll"; 47*4882a593Smuzhiyun #clock-cells = <1>; 48*4882a593Smuzhiyun clocks = <&lcpll_clk>; 49*4882a593Smuzhiyun reg = <0x1110000c 0x24>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun... 53