1*4882a593SmuzhiyunDevicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis device exposes 4 clocks in total: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz 6*4882a593Smuzhiyun- MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete 7*4882a593Smuzhiyun frequencies 8*4882a593Smuzhiyun- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunMAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set 11*4882a593Smuzhiyunrequests. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunRequired properties: 14*4882a593Smuzhiyun- compatible: "maxim,max9485" 15*4882a593Smuzhiyun- clocks: Input clock, must provice 27.000 MHz 16*4882a593Smuzhiyun- clock-names: Must be set to "xclk" 17*4882a593Smuzhiyun- #clock-cells: From common clock binding; shall be set to 1 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional properties: 20*4882a593Smuzhiyun- reset-gpios: GPIO descriptor connected to the #RESET input pin 21*4882a593Smuzhiyun- vdd-supply: A regulator node for Vdd 22*4882a593Smuzhiyun- clock-output-names: Name of output clocks, as defined in common clock 23*4882a593Smuzhiyun bindings 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunIf not explicitly set, the output names are "mclkout", "clkout", "clkout1" 26*4882a593Smuzhiyunand "clkout2". 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunClocks are defined as preprocessor macros in the dt-binding header. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExample: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #include <dt-bindings/clock/maxim,max9485.h> 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun xo-27mhz: xo-27mhz { 35*4882a593Smuzhiyun compatible = "fixed-clock"; 36*4882a593Smuzhiyun #clock-cells = <0>; 37*4882a593Smuzhiyun clock-frequency = <27000000>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun &i2c0 { 41*4882a593Smuzhiyun max9485: audio-clock@63 { 42*4882a593Smuzhiyun reg = <0x63>; 43*4882a593Smuzhiyun compatible = "maxim,max9485"; 44*4882a593Smuzhiyun clock-names = "xclk"; 45*4882a593Smuzhiyun clocks = <&xo-27mhz>; 46*4882a593Smuzhiyun reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; 47*4882a593Smuzhiyun vdd-supply = <&3v3-reg>; 48*4882a593Smuzhiyun #clock-cells = <1>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun // Clock consumer node 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun foo@0 { 55*4882a593Smuzhiyun compatible = "bar,foo"; 56*4882a593Smuzhiyun /* ... */ 57*4882a593Smuzhiyun clock-names = "foo-input-clk"; 58*4882a593Smuzhiyun clocks = <&max9485 MAX9485_CLKOUT1>; 59*4882a593Smuzhiyun }; 60