1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Marvell MMP2 and MMP3 Clock Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Lubomir Rintel <lkundrak@v3.sk> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The clock subsystem on MMP2 or MMP3 generates and supplies clock to various 14*4882a593Smuzhiyun controllers within the SoC. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun Each clock is assigned an identifier and client nodes use this identifier 17*4882a593Smuzhiyun to specify the clock which they consume. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunproperties: 22*4882a593Smuzhiyun compatible: 23*4882a593Smuzhiyun enum: 24*4882a593Smuzhiyun - marvell,mmp2-clock # controller compatible with MMP2 SoC 25*4882a593Smuzhiyun - marvell,mmp3-clock # controller compatible with MMP3 SoC 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg: 28*4882a593Smuzhiyun items: 29*4882a593Smuzhiyun - description: MPMU register region 30*4882a593Smuzhiyun - description: APMU register region 31*4882a593Smuzhiyun - description: APBC register region 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun reg-names: 34*4882a593Smuzhiyun items: 35*4882a593Smuzhiyun - const: mpmu 36*4882a593Smuzhiyun - const: apmu 37*4882a593Smuzhiyun - const: apbc 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun '#clock-cells': 40*4882a593Smuzhiyun const: 1 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun '#reset-cells': 43*4882a593Smuzhiyun const: 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun '#power-domain-cells': 46*4882a593Smuzhiyun const: 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunrequired: 49*4882a593Smuzhiyun - compatible 50*4882a593Smuzhiyun - reg 51*4882a593Smuzhiyun - reg-names 52*4882a593Smuzhiyun - '#clock-cells' 53*4882a593Smuzhiyun - '#reset-cells' 54*4882a593Smuzhiyun - '#power-domain-cells' 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunadditionalProperties: false 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunexamples: 59*4882a593Smuzhiyun - | 60*4882a593Smuzhiyun clock-controller@d4050000 { 61*4882a593Smuzhiyun compatible = "marvell,mmp2-clock"; 62*4882a593Smuzhiyun reg = <0xd4050000 0x1000>, 63*4882a593Smuzhiyun <0xd4282800 0x400>, 64*4882a593Smuzhiyun <0xd4015000 0x1000>; 65*4882a593Smuzhiyun reg-names = "mpmu", "apmu", "apbc"; 66*4882a593Smuzhiyun #clock-cells = <1>; 67*4882a593Smuzhiyun #reset-cells = <1>; 68*4882a593Smuzhiyun #power-domain-cells = <1>; 69*4882a593Smuzhiyun }; 70