1*4882a593Smuzhiyun* Marvell PXA910 Clock Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe PXA910 clock subsystem generates and supplies clock to various 4*4882a593Smuzhiyuncontrollers within the PXA910 SoC. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: should be one of the following. 9*4882a593Smuzhiyun - "marvell,pxa910-clock" - controller compatible with PXA910 SoC. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- reg: physical base address of the clock subsystem and length of memory mapped 12*4882a593Smuzhiyun region. There are 4 places in SOC has clock control logic: 13*4882a593Smuzhiyun "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- #clock-cells: should be 1. 16*4882a593Smuzhiyun- #reset-cells: should be 1. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes use this identifier 19*4882a593Smuzhiyunto specify the clock which they consume. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunAll these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>. 22