1*4882a593SmuzhiyunDevice Tree Clock bindings for Marvell Berlin 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunClock related registers are spread among the chip control registers. Berlin 8*4882a593Smuzhiyunclock node should be a sub-node of the chip controller node. Marvell Berlin2 9*4882a593Smuzhiyun(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some 10*4882a593Smuzhiyunminor differences in features and register layout. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired properties: 13*4882a593Smuzhiyun- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk" 14*4882a593Smuzhiyun- #clock-cells: must be 1 15*4882a593Smuzhiyun- clocks: must be the input parent clock phandle 16*4882a593Smuzhiyun- clock-names: name of the input parent clock 17*4882a593Smuzhiyun Allowed clock-names for the reference clocks are 18*4882a593Smuzhiyun "refclk" for the SoCs oscillator input on all SoCs, 19*4882a593Smuzhiyun and SoC-specific input clocks for 20*4882a593Smuzhiyun BG2/BG2CD: "video_ext0" for the external video clock input 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunchip_clk: clock { 26*4882a593Smuzhiyun compatible = "marvell,berlin2q-clk"; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #clock-cells = <1>; 29*4882a593Smuzhiyun clocks = <&refclk>; 30*4882a593Smuzhiyun clock-names = "refclk"; 31*4882a593Smuzhiyun}; 32