xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* NXP LPC1850 CREG clocks
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThe NXP LPC18xx/43xx CREG (Configuration Registers) block contains
4*4882a593Smuzhiyuncontrol registers for two low speed clocks. One of the clocks is a
5*4882a593Smuzhiyun32 kHz oscillator driver with power up/down and clock gating. Next
6*4882a593Smuzhiyunis a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
7*4882a593Smuzhiyun
8*4882a593SmuzhiyunThese clocks are used by the RTC and the Event Router peripherials.
9*4882a593SmuzhiyunThe 32 kHz can also be routed to other peripherials to enable low
10*4882a593Smuzhiyunpower modes.
11*4882a593Smuzhiyun
12*4882a593SmuzhiyunThis binding uses the common clock binding:
13*4882a593Smuzhiyun    Documentation/devicetree/bindings/clock/clock-bindings.txt
14*4882a593Smuzhiyun
15*4882a593SmuzhiyunRequired properties:
16*4882a593Smuzhiyun- compatible:
17*4882a593Smuzhiyun	Should be "nxp,lpc1850-creg-clk"
18*4882a593Smuzhiyun- #clock-cells:
19*4882a593Smuzhiyun	Shall have value <1>.
20*4882a593Smuzhiyun- clocks:
21*4882a593Smuzhiyun	Shall contain a phandle to the fixed 32 kHz crystal.
22*4882a593Smuzhiyun
23*4882a593SmuzhiyunThe creg-clk node must be a child of the creg syscon node.
24*4882a593Smuzhiyun
25*4882a593SmuzhiyunThe following clocks are available from the clock node.
26*4882a593Smuzhiyun
27*4882a593SmuzhiyunClock ID	Name
28*4882a593Smuzhiyun   0		 1 kHz clock
29*4882a593Smuzhiyun   1		32 kHz Oscillator
30*4882a593Smuzhiyun
31*4882a593SmuzhiyunExample:
32*4882a593Smuzhiyunsoc {
33*4882a593Smuzhiyun	creg: syscon@40043000 {
34*4882a593Smuzhiyun		compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
35*4882a593Smuzhiyun		reg = <0x40043000 0x1000>;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun		creg_clk: clock-controller {
38*4882a593Smuzhiyun			compatible = "nxp,lpc1850-creg-clk";
39*4882a593Smuzhiyun			clocks = <&xtal32>;
40*4882a593Smuzhiyun			#clock-cells = <1>;
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		...
44*4882a593Smuzhiyun	};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	rtc: rtc@40046000 {
47*4882a593Smuzhiyun		...
48*4882a593Smuzhiyun		clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
49*4882a593Smuzhiyun		clock-names = "rtc", "reg";
50*4882a593Smuzhiyun		...
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun};
53