1*4882a593SmuzhiyunDevice Tree Clock bindings for Intel's SoCFPGA Stratix10 platform 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible : shall be 9*4882a593Smuzhiyun "intel,stratix10-clkmgr" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- #clock-cells : from common clock binding, shall be set to 1. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun clkmgr: clock-controller@ffd10000 { 17*4882a593Smuzhiyun compatible = "intel,stratix10-clkmgr"; 18*4882a593Smuzhiyun reg = <0xffd10000 0x1000>; 19*4882a593Smuzhiyun #clock-cells = <1>; 20*4882a593Smuzhiyun }; 21