1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Clock bindings for Freescale i.MX6 SoloX 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Anson Huang <Anson.Huang@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun const: fsl,imx6sx-ccm 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun reg: 17*4882a593Smuzhiyun maxItems: 1 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun interrupts: 20*4882a593Smuzhiyun description: CCM provides 2 interrupt requests, request 1 is to generate 21*4882a593Smuzhiyun interrupt for frequency or mux change, request 2 is to generate 22*4882a593Smuzhiyun interrupt for oscillator read or PLL lock. 23*4882a593Smuzhiyun items: 24*4882a593Smuzhiyun - description: CCM interrupt request 1 25*4882a593Smuzhiyun - description: CCM interrupt request 2 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun '#clock-cells': 28*4882a593Smuzhiyun const: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks: 31*4882a593Smuzhiyun items: 32*4882a593Smuzhiyun - description: 32k osc 33*4882a593Smuzhiyun - description: 24m osc 34*4882a593Smuzhiyun - description: ipp_di0 clock input 35*4882a593Smuzhiyun - description: ipp_di1 clock input 36*4882a593Smuzhiyun - description: anaclk1 clock input 37*4882a593Smuzhiyun - description: anaclk2 clock input 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun clock-names: 40*4882a593Smuzhiyun items: 41*4882a593Smuzhiyun - const: ckil 42*4882a593Smuzhiyun - const: osc 43*4882a593Smuzhiyun - const: ipp_di0 44*4882a593Smuzhiyun - const: ipp_di1 45*4882a593Smuzhiyun - const: anaclk1 46*4882a593Smuzhiyun - const: anaclk2 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunrequired: 49*4882a593Smuzhiyun - compatible 50*4882a593Smuzhiyun - reg 51*4882a593Smuzhiyun - interrupts 52*4882a593Smuzhiyun - '#clock-cells' 53*4882a593Smuzhiyun - clocks 54*4882a593Smuzhiyun - clock-names 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunadditionalProperties: false 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunexamples: 59*4882a593Smuzhiyun # Clock Control Module node: 60*4882a593Smuzhiyun - | 61*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun clock-controller@20c4000 { 64*4882a593Smuzhiyun compatible = "fsl,imx6sx-ccm"; 65*4882a593Smuzhiyun reg = <0x020c4000 0x4000>; 66*4882a593Smuzhiyun interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 67*4882a593Smuzhiyun <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 68*4882a593Smuzhiyun #clock-cells = <1>; 69*4882a593Smuzhiyun clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; 70*4882a593Smuzhiyun clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; 71*4882a593Smuzhiyun }; 72