1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/imx5-clock.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Clock bindings for Freescale i.MX5 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Fabio Estevam <fabio.estevam@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The clock consumer should specify the desired clock by having the clock 14*4882a593Smuzhiyun ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h 15*4882a593Smuzhiyun for the full list of i.MX5 clock IDs. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun enum: 20*4882a593Smuzhiyun - fsl,imx53-ccm 21*4882a593Smuzhiyun - fsl,imx51-ccm 22*4882a593Smuzhiyun - fsl,imx50-ccm 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun reg: 25*4882a593Smuzhiyun maxItems: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun interrupts: 28*4882a593Smuzhiyun description: CCM provides 2 interrupt requests, request 1 is to generate 29*4882a593Smuzhiyun interrupt for frequency or mux change, request 2 is to generate 30*4882a593Smuzhiyun interrupt for oscillator read or PLL lock. 31*4882a593Smuzhiyun items: 32*4882a593Smuzhiyun - description: CCM interrupt request 1 33*4882a593Smuzhiyun - description: CCM interrupt request 2 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun '#clock-cells': 36*4882a593Smuzhiyun const: 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyunrequired: 39*4882a593Smuzhiyun - compatible 40*4882a593Smuzhiyun - reg 41*4882a593Smuzhiyun - interrupts 42*4882a593Smuzhiyun - '#clock-cells' 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunadditionalProperties: false 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunexamples: 47*4882a593Smuzhiyun - | 48*4882a593Smuzhiyun #include <dt-bindings/clock/imx5-clock.h> 49*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun clock-controller@53fd4000{ 52*4882a593Smuzhiyun compatible = "fsl,imx53-ccm"; 53*4882a593Smuzhiyun reg = <0x53fd4000 0x4000>; 54*4882a593Smuzhiyun interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, 55*4882a593Smuzhiyun <0 72 IRQ_TYPE_LEVEL_HIGH>; 56*4882a593Smuzhiyun #clock-cells = <1>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun can@53fc8000 { 60*4882a593Smuzhiyun compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; 61*4882a593Smuzhiyun reg = <0x53fc8000 0x4000>; 62*4882a593Smuzhiyun interrupts = <82>; 63*4882a593Smuzhiyun clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>; 64*4882a593Smuzhiyun clock-names = "ipg", "per"; 65*4882a593Smuzhiyun }; 66