1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/imx28-clock.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Clock bindings for Freescale i.MX28 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Shawn Guo <shawnguo@kernel.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The clock consumer should specify the desired clock by having the clock 14*4882a593Smuzhiyun ID in its "clocks" phandle cell. The following is a full list of i.MX28 15*4882a593Smuzhiyun clocks and IDs. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun Clock ID 18*4882a593Smuzhiyun ------------------ 19*4882a593Smuzhiyun ref_xtal 0 20*4882a593Smuzhiyun pll0 1 21*4882a593Smuzhiyun pll1 2 22*4882a593Smuzhiyun pll2 3 23*4882a593Smuzhiyun ref_cpu 4 24*4882a593Smuzhiyun ref_emi 5 25*4882a593Smuzhiyun ref_io0 6 26*4882a593Smuzhiyun ref_io1 7 27*4882a593Smuzhiyun ref_pix 8 28*4882a593Smuzhiyun ref_hsadc 9 29*4882a593Smuzhiyun ref_gpmi 10 30*4882a593Smuzhiyun saif0_sel 11 31*4882a593Smuzhiyun saif1_sel 12 32*4882a593Smuzhiyun gpmi_sel 13 33*4882a593Smuzhiyun ssp0_sel 14 34*4882a593Smuzhiyun ssp1_sel 15 35*4882a593Smuzhiyun ssp2_sel 16 36*4882a593Smuzhiyun ssp3_sel 17 37*4882a593Smuzhiyun emi_sel 18 38*4882a593Smuzhiyun etm_sel 19 39*4882a593Smuzhiyun lcdif_sel 20 40*4882a593Smuzhiyun cpu 21 41*4882a593Smuzhiyun ptp_sel 22 42*4882a593Smuzhiyun cpu_pll 23 43*4882a593Smuzhiyun cpu_xtal 24 44*4882a593Smuzhiyun hbus 25 45*4882a593Smuzhiyun xbus 26 46*4882a593Smuzhiyun ssp0_div 27 47*4882a593Smuzhiyun ssp1_div 28 48*4882a593Smuzhiyun ssp2_div 29 49*4882a593Smuzhiyun ssp3_div 30 50*4882a593Smuzhiyun gpmi_div 31 51*4882a593Smuzhiyun emi_pll 32 52*4882a593Smuzhiyun emi_xtal 33 53*4882a593Smuzhiyun lcdif_div 34 54*4882a593Smuzhiyun etm_div 35 55*4882a593Smuzhiyun ptp 36 56*4882a593Smuzhiyun saif0_div 37 57*4882a593Smuzhiyun saif1_div 38 58*4882a593Smuzhiyun clk32k_div 39 59*4882a593Smuzhiyun rtc 40 60*4882a593Smuzhiyun lradc 41 61*4882a593Smuzhiyun spdif_div 42 62*4882a593Smuzhiyun clk32k 43 63*4882a593Smuzhiyun pwm 44 64*4882a593Smuzhiyun uart 45 65*4882a593Smuzhiyun ssp0 46 66*4882a593Smuzhiyun ssp1 47 67*4882a593Smuzhiyun ssp2 48 68*4882a593Smuzhiyun ssp3 49 69*4882a593Smuzhiyun gpmi 50 70*4882a593Smuzhiyun spdif 51 71*4882a593Smuzhiyun emi 52 72*4882a593Smuzhiyun saif0 53 73*4882a593Smuzhiyun saif1 54 74*4882a593Smuzhiyun lcdif 55 75*4882a593Smuzhiyun etm 56 76*4882a593Smuzhiyun fec 57 77*4882a593Smuzhiyun can0 58 78*4882a593Smuzhiyun can1 59 79*4882a593Smuzhiyun usb0 60 80*4882a593Smuzhiyun usb1 61 81*4882a593Smuzhiyun usb0_phy 62 82*4882a593Smuzhiyun usb1_phy 63 83*4882a593Smuzhiyun enet_out 64 84*4882a593Smuzhiyun 85*4882a593Smuzhiyunproperties: 86*4882a593Smuzhiyun compatible: 87*4882a593Smuzhiyun const: fsl,imx28-clkctrl 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun reg: 90*4882a593Smuzhiyun maxItems: 1 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun '#clock-cells': 93*4882a593Smuzhiyun const: 1 94*4882a593Smuzhiyun 95*4882a593Smuzhiyunrequired: 96*4882a593Smuzhiyun - compatible 97*4882a593Smuzhiyun - reg 98*4882a593Smuzhiyun - '#clock-cells' 99*4882a593Smuzhiyun 100*4882a593SmuzhiyunadditionalProperties: false 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunexamples: 103*4882a593Smuzhiyun - | 104*4882a593Smuzhiyun clock-controller@80040000 { 105*4882a593Smuzhiyun compatible = "fsl,imx28-clkctrl"; 106*4882a593Smuzhiyun reg = <0x80040000 0x2000>; 107*4882a593Smuzhiyun #clock-cells = <1>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun serial@8006a000 { 111*4882a593Smuzhiyun compatible = "fsl,imx28-auart"; 112*4882a593Smuzhiyun reg = <0x8006a000 0x2000>; 113*4882a593Smuzhiyun interrupts = <112>; 114*4882a593Smuzhiyun dmas = <&dma_apbx 8>, <&dma_apbx 9>; 115*4882a593Smuzhiyun dma-names = "rx", "tx"; 116*4882a593Smuzhiyun clocks = <&clks 45>; 117*4882a593Smuzhiyun }; 118