1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/imx23-clock.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Clock bindings for Freescale i.MX23 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Shawn Guo <shawnguo@kernel.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The clock consumer should specify the desired clock by having the clock 14*4882a593Smuzhiyun ID in its "clocks" phandle cell. The following is a full list of i.MX23 15*4882a593Smuzhiyun clocks and IDs. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun Clock ID 18*4882a593Smuzhiyun ------------------ 19*4882a593Smuzhiyun ref_xtal 0 20*4882a593Smuzhiyun pll 1 21*4882a593Smuzhiyun ref_cpu 2 22*4882a593Smuzhiyun ref_emi 3 23*4882a593Smuzhiyun ref_pix 4 24*4882a593Smuzhiyun ref_io 5 25*4882a593Smuzhiyun saif_sel 6 26*4882a593Smuzhiyun lcdif_sel 7 27*4882a593Smuzhiyun gpmi_sel 8 28*4882a593Smuzhiyun ssp_sel 9 29*4882a593Smuzhiyun emi_sel 10 30*4882a593Smuzhiyun cpu 11 31*4882a593Smuzhiyun etm_sel 12 32*4882a593Smuzhiyun cpu_pll 13 33*4882a593Smuzhiyun cpu_xtal 14 34*4882a593Smuzhiyun hbus 15 35*4882a593Smuzhiyun xbus 16 36*4882a593Smuzhiyun lcdif_div 17 37*4882a593Smuzhiyun ssp_div 18 38*4882a593Smuzhiyun gpmi_div 19 39*4882a593Smuzhiyun emi_pll 20 40*4882a593Smuzhiyun emi_xtal 21 41*4882a593Smuzhiyun etm_div 22 42*4882a593Smuzhiyun saif_div 23 43*4882a593Smuzhiyun clk32k_div 24 44*4882a593Smuzhiyun rtc 25 45*4882a593Smuzhiyun adc 26 46*4882a593Smuzhiyun spdif_div 27 47*4882a593Smuzhiyun clk32k 28 48*4882a593Smuzhiyun dri 29 49*4882a593Smuzhiyun pwm 30 50*4882a593Smuzhiyun filt 31 51*4882a593Smuzhiyun uart 32 52*4882a593Smuzhiyun ssp 33 53*4882a593Smuzhiyun gpmi 34 54*4882a593Smuzhiyun spdif 35 55*4882a593Smuzhiyun emi 36 56*4882a593Smuzhiyun saif 37 57*4882a593Smuzhiyun lcdif 38 58*4882a593Smuzhiyun etm 39 59*4882a593Smuzhiyun usb 40 60*4882a593Smuzhiyun usb_phy 41 61*4882a593Smuzhiyun 62*4882a593Smuzhiyunproperties: 63*4882a593Smuzhiyun compatible: 64*4882a593Smuzhiyun const: fsl,imx23-clkctrl 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun reg: 67*4882a593Smuzhiyun maxItems: 1 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun '#clock-cells': 70*4882a593Smuzhiyun const: 1 71*4882a593Smuzhiyun 72*4882a593Smuzhiyunrequired: 73*4882a593Smuzhiyun - compatible 74*4882a593Smuzhiyun - reg 75*4882a593Smuzhiyun - '#clock-cells' 76*4882a593Smuzhiyun 77*4882a593SmuzhiyunadditionalProperties: false 78*4882a593Smuzhiyun 79*4882a593Smuzhiyunexamples: 80*4882a593Smuzhiyun - | 81*4882a593Smuzhiyun clock-controller@80040000 { 82*4882a593Smuzhiyun compatible = "fsl,imx23-clkctrl"; 83*4882a593Smuzhiyun reg = <0x80040000 0x2000>; 84*4882a593Smuzhiyun #clock-cells = <1>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun serial@8006c000 { 88*4882a593Smuzhiyun compatible = "fsl,imx23-auart"; 89*4882a593Smuzhiyun reg = <0x8006c000 0x2000>; 90*4882a593Smuzhiyun interrupts = <24>; 91*4882a593Smuzhiyun clocks = <&clks 32>; 92*4882a593Smuzhiyun dmas = <&dma_apbx 6>, <&dma_apbx 7>; 93*4882a593Smuzhiyun dma-names = "rx", "tx"; 94*4882a593Smuzhiyun }; 95