xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/imx21-clock.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/imx21-clock.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Clock bindings for Freescale i.MX21
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Alexander Shiyan <shc_work@mail.ru>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription: |
13*4882a593Smuzhiyun  The clock consumer should specify the desired clock by having the clock
14*4882a593Smuzhiyun  ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
15*4882a593Smuzhiyun  for the full list of i.MX21 clock IDs.
16*4882a593Smuzhiyun
17*4882a593Smuzhiyunproperties:
18*4882a593Smuzhiyun  compatible:
19*4882a593Smuzhiyun    const: fsl,imx21-ccm
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun  reg:
22*4882a593Smuzhiyun    maxItems: 1
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun  '#clock-cells':
25*4882a593Smuzhiyun    const: 1
26*4882a593Smuzhiyun
27*4882a593Smuzhiyunrequired:
28*4882a593Smuzhiyun  - compatible
29*4882a593Smuzhiyun  - reg
30*4882a593Smuzhiyun  - '#clock-cells'
31*4882a593Smuzhiyun
32*4882a593SmuzhiyunadditionalProperties: false
33*4882a593Smuzhiyun
34*4882a593Smuzhiyunexamples:
35*4882a593Smuzhiyun  - |
36*4882a593Smuzhiyun    #include <dt-bindings/clock/imx21-clock.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun    clock-controller@10027000 {
39*4882a593Smuzhiyun        compatible = "fsl,imx21-ccm";
40*4882a593Smuzhiyun        reg = <0x10027000 0x800>;
41*4882a593Smuzhiyun        #clock-cells = <1>;
42*4882a593Smuzhiyun    };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun    serial@1000a000 {
45*4882a593Smuzhiyun        compatible = "fsl,imx21-uart";
46*4882a593Smuzhiyun        reg = <0x1000a000 0x1000>;
47*4882a593Smuzhiyun        interrupts = <20>;
48*4882a593Smuzhiyun        clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
49*4882a593Smuzhiyun                 <&clks IMX21_CLK_PER1>;
50*4882a593Smuzhiyun        clock-names = "ipg", "per";
51*4882a593Smuzhiyun    };
52