xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
8*4882a593Smuzhiyun
9*4882a593Smuzhiyundescription: |
10*4882a593Smuzhiyun  The IDT VersaClock 5 and VersaClock 6 are programmable I2C
11*4882a593Smuzhiyun  clock generators providing from 3 to 12 output clocks.
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun  When referencing the provided clock in the DT using phandle and clock
14*4882a593Smuzhiyun  specifier, the following mapping applies:
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun  - 5P49V5923:
17*4882a593Smuzhiyun    0 -- OUT0_SEL_I2CB
18*4882a593Smuzhiyun    1 -- OUT1
19*4882a593Smuzhiyun    2 -- OUT2
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun  - 5P49V5933:
22*4882a593Smuzhiyun    0 -- OUT0_SEL_I2CB
23*4882a593Smuzhiyun    1 -- OUT1
24*4882a593Smuzhiyun    2 -- OUT4
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  - other parts:
27*4882a593Smuzhiyun    0 -- OUT0_SEL_I2CB
28*4882a593Smuzhiyun    1 -- OUT1
29*4882a593Smuzhiyun    2 -- OUT2
30*4882a593Smuzhiyun    3 -- OUT3
31*4882a593Smuzhiyun    4 -- OUT4
32*4882a593Smuzhiyun
33*4882a593Smuzhiyunmaintainers:
34*4882a593Smuzhiyun  - Luca Ceresoli <luca@lucaceresoli.net>
35*4882a593Smuzhiyun
36*4882a593Smuzhiyunproperties:
37*4882a593Smuzhiyun  compatible:
38*4882a593Smuzhiyun    enum:
39*4882a593Smuzhiyun      - idt,5p49v5923
40*4882a593Smuzhiyun      - idt,5p49v5925
41*4882a593Smuzhiyun      - idt,5p49v5933
42*4882a593Smuzhiyun      - idt,5p49v5935
43*4882a593Smuzhiyun      - idt,5p49v6901
44*4882a593Smuzhiyun      - idt,5p49v6965
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun  reg:
47*4882a593Smuzhiyun    description: I2C device address
48*4882a593Smuzhiyun    enum: [ 0x68, 0x6a ]
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun  '#clock-cells':
51*4882a593Smuzhiyun    const: 1
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  clock-names:
54*4882a593Smuzhiyun    minItems: 1
55*4882a593Smuzhiyun    maxItems: 2
56*4882a593Smuzhiyun    items:
57*4882a593Smuzhiyun      enum: [ xin, clkin ]
58*4882a593Smuzhiyun  clocks:
59*4882a593Smuzhiyun    minItems: 1
60*4882a593Smuzhiyun    maxItems: 2
61*4882a593Smuzhiyun
62*4882a593SmuzhiyunpatternProperties:
63*4882a593Smuzhiyun  "^OUT[1-4]$":
64*4882a593Smuzhiyun    type: object
65*4882a593Smuzhiyun    description:
66*4882a593Smuzhiyun      Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
67*4882a593Smuzhiyun      Configuration" in the Versaclock 5/6/6E Family Register Description
68*4882a593Smuzhiyun      and Programming Guide.
69*4882a593Smuzhiyun    properties:
70*4882a593Smuzhiyun      idt,mode:
71*4882a593Smuzhiyun        description:
72*4882a593Smuzhiyun          The output drive mode. Values defined in dt-bindings/clk/versaclock.h
73*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/uint32
74*4882a593Smuzhiyun        minimum: 0
75*4882a593Smuzhiyun        maximum: 6
76*4882a593Smuzhiyun      idt,voltage-microvolt:
77*4882a593Smuzhiyun        description: The output drive voltage.
78*4882a593Smuzhiyun        enum: [ 1800000, 2500000, 3300000 ]
79*4882a593Smuzhiyun      idt,slew-percent:
80*4882a593Smuzhiyun        description: The Slew rate control for CMOS single-ended.
81*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/uint32
82*4882a593Smuzhiyun        enum: [ 80, 85, 90, 100 ]
83*4882a593Smuzhiyun
84*4882a593Smuzhiyunrequired:
85*4882a593Smuzhiyun  - compatible
86*4882a593Smuzhiyun  - reg
87*4882a593Smuzhiyun  - '#clock-cells'
88*4882a593Smuzhiyun
89*4882a593SmuzhiyunallOf:
90*4882a593Smuzhiyun  - if:
91*4882a593Smuzhiyun      properties:
92*4882a593Smuzhiyun        compatible:
93*4882a593Smuzhiyun          enum:
94*4882a593Smuzhiyun            - idt,5p49v5933
95*4882a593Smuzhiyun            - idt,5p49v5935
96*4882a593Smuzhiyun    then:
97*4882a593Smuzhiyun      # Devices with builtin crystal + optional external input
98*4882a593Smuzhiyun      properties:
99*4882a593Smuzhiyun        clock-names:
100*4882a593Smuzhiyun          const: clkin
101*4882a593Smuzhiyun        clocks:
102*4882a593Smuzhiyun          maxItems: 1
103*4882a593Smuzhiyun    else:
104*4882a593Smuzhiyun      # Devices without builtin crystal
105*4882a593Smuzhiyun      required:
106*4882a593Smuzhiyun        - clock-names
107*4882a593Smuzhiyun        - clocks
108*4882a593Smuzhiyun
109*4882a593SmuzhiyunadditionalProperties: false
110*4882a593Smuzhiyun
111*4882a593Smuzhiyunexamples:
112*4882a593Smuzhiyun  - |
113*4882a593Smuzhiyun    #include <dt-bindings/clk/versaclock.h>
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun    /* 25MHz reference crystal */
116*4882a593Smuzhiyun    ref25: ref25m {
117*4882a593Smuzhiyun        compatible = "fixed-clock";
118*4882a593Smuzhiyun        #clock-cells = <0>;
119*4882a593Smuzhiyun        clock-frequency = <25000000>;
120*4882a593Smuzhiyun    };
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun    i2c@0 {
123*4882a593Smuzhiyun        reg = <0x0 0x100>;
124*4882a593Smuzhiyun        #address-cells = <1>;
125*4882a593Smuzhiyun        #size-cells = <0>;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun        /* IDT 5P49V5923 I2C clock generator */
128*4882a593Smuzhiyun        vc5: clock-generator@6a {
129*4882a593Smuzhiyun            compatible = "idt,5p49v5923";
130*4882a593Smuzhiyun            reg = <0x6a>;
131*4882a593Smuzhiyun            #clock-cells = <1>;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun            /* Connect XIN input to 25MHz reference */
134*4882a593Smuzhiyun            clocks = <&ref25m>;
135*4882a593Smuzhiyun            clock-names = "xin";
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun            OUT1 {
138*4882a593Smuzhiyun                idt,drive-mode = <VC5_CMOSD>;
139*4882a593Smuzhiyun                idt,voltage-microvolts = <1800000>;
140*4882a593Smuzhiyun                idt,slew-percent = <80>;
141*4882a593Smuzhiyun            };
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun            OUT4 {
144*4882a593Smuzhiyun                idt,drive-mode = <VC5_LVDS>;
145*4882a593Smuzhiyun            };
146*4882a593Smuzhiyun        };
147*4882a593Smuzhiyun    };
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun    /* Consumer referencing the 5P49V5923 pin OUT1 */
150*4882a593Smuzhiyun    consumer {
151*4882a593Smuzhiyun        /* ... */
152*4882a593Smuzhiyun        clocks = <&vc5 1>;
153*4882a593Smuzhiyun        /* ... */
154*4882a593Smuzhiyun    };
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun...
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