1*4882a593Smuzhiyun* Hisilicon Hix5hd2 Clock Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe hix5hd2 clock controller generates and supplies clock to various 4*4882a593Smuzhiyuncontrollers within the hix5hd2 SoC. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: should be "hisilicon,hix5hd2-clock" 9*4882a593Smuzhiyun- reg: Address and length of the register set 10*4882a593Smuzhiyun- #clock-cells: Should be <1> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes use this identifier 13*4882a593Smuzhiyunto specify the clock which they consume. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunAll these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExamples: 18*4882a593Smuzhiyun clock: clock@f8a22000 { 19*4882a593Smuzhiyun compatible = "hisilicon,hix5hd2-clock"; 20*4882a593Smuzhiyun reg = <0xf8a22000 0x1000>; 21*4882a593Smuzhiyun #clock-cells = <1>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun uart0: uart@f8b00000 { 25*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 26*4882a593Smuzhiyun reg = <0xf8b00000 0x1000>; 27*4882a593Smuzhiyun interrupts = <0 49 4>; 28*4882a593Smuzhiyun clocks = <&clock HIX5HD2_FIXED_83M>; 29*4882a593Smuzhiyun clock-names = "apb_pclk"; 30*4882a593Smuzhiyun }; 31