1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Wen He <wen.he_1@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun NXP LS1028A has a clock domain PXLCLK0 used for the Display output 14*4882a593Smuzhiyun interface in the display core, as implemented in TSMC CLN28HPM PLL. 15*4882a593Smuzhiyun which generate and offers pixel clocks to Display. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun const: fsl,ls1028a-plldig 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun reg: 22*4882a593Smuzhiyun maxItems: 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun clocks: 25*4882a593Smuzhiyun maxItems: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun '#clock-cells': 28*4882a593Smuzhiyun const: 0 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun fsl,vco-hz: 31*4882a593Smuzhiyun description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency 32*4882a593Smuzhiyun of this PLL cannot be changed during runtime only at startup. Therefore, 33*4882a593Smuzhiyun the output frequencies are very limited and might not even closely match 34*4882a593Smuzhiyun the requested frequency. To work around this restriction the user may specify 35*4882a593Smuzhiyun its own desired VCO frequency for the PLL. 36*4882a593Smuzhiyun minimum: 650000000 37*4882a593Smuzhiyun maximum: 1300000000 38*4882a593Smuzhiyun default: 1188000000 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunrequired: 41*4882a593Smuzhiyun - compatible 42*4882a593Smuzhiyun - reg 43*4882a593Smuzhiyun - clocks 44*4882a593Smuzhiyun - '#clock-cells' 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunadditionalProperties: false 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunexamples: 49*4882a593Smuzhiyun # Display PIXEL Clock node: 50*4882a593Smuzhiyun - | 51*4882a593Smuzhiyun dpclk: clock-display@f1f0000 { 52*4882a593Smuzhiyun compatible = "fsl,ls1028a-plldig"; 53*4882a593Smuzhiyun reg = <0xf1f0000 0xffff>; 54*4882a593Smuzhiyun #clock-cells = <0>; 55*4882a593Smuzhiyun clocks = <&osc_27m>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun... 59