1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale SAI bitclock-as-a-clock binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Michael Walle <michael@walle.cc> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun It is possible to use the BCLK pin of a SAI module as a generic clock 14*4882a593Smuzhiyun output. Some SoC are very constrained in their pin multiplexer 15*4882a593Smuzhiyun configuration. Eg. pins can only be changed groups. For example, on the 16*4882a593Smuzhiyun LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI, 17*4882a593Smuzhiyun the second pins are wasted. Using this binding it is possible to use the 18*4882a593Smuzhiyun clock of the second SAI as a MCLK clock for an audio codec, for example. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun This is a composite of a gated clock and a divider clock. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunproperties: 23*4882a593Smuzhiyun compatible: 24*4882a593Smuzhiyun const: fsl,vf610-sai-clock 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun reg: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clocks: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun '#clock-cells': 33*4882a593Smuzhiyun const: 0 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunrequired: 36*4882a593Smuzhiyun - compatible 37*4882a593Smuzhiyun - reg 38*4882a593Smuzhiyun - clocks 39*4882a593Smuzhiyun - '#clock-cells' 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunadditionalProperties: false 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunexamples: 44*4882a593Smuzhiyun - | 45*4882a593Smuzhiyun soc { 46*4882a593Smuzhiyun #address-cells = <2>; 47*4882a593Smuzhiyun #size-cells = <2>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun mclk: clock-mclk@f130080 { 50*4882a593Smuzhiyun compatible = "fsl,vf610-sai-clock"; 51*4882a593Smuzhiyun reg = <0x0 0xf130080 0x0 0x80>; 52*4882a593Smuzhiyun #clock-cells = <0>; 53*4882a593Smuzhiyun clocks = <&parentclk>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56