1*4882a593Smuzhiyun* Samsung Exynos7 Clock Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunExynos7 clock controller has various blocks which are instantiated 4*4882a593Smuzhiyunindependently from the device-tree. These clock controllers 5*4882a593Smuzhiyungenerate and supply clocks to various hardware blocks within 6*4882a593Smuzhiyunthe SoC. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes can use 9*4882a593Smuzhiyunthis identifier to specify the clock which they consume. All 10*4882a593Smuzhiyunavailable clocks are defined as preprocessor macros in 11*4882a593Smuzhiyundt-bindings/clock/exynos7-clk.h header and can be used in 12*4882a593Smuzhiyundevice tree sources. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunExternal clocks: 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunThere are several clocks that are generated outside the SoC. It 17*4882a593Smuzhiyunis expected that they are defined using standard clock bindings 18*4882a593Smuzhiyunwith following clock-output-names: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun - "fin_pll" - PLL input clock from XXTI 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunRequired Properties for Clock Controller: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun - compatible: clock controllers will use one of the following 25*4882a593Smuzhiyun compatible strings to indicate the clock controller 26*4882a593Smuzhiyun functionality. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun - "samsung,exynos7-clock-topc" 29*4882a593Smuzhiyun - "samsung,exynos7-clock-top0" 30*4882a593Smuzhiyun - "samsung,exynos7-clock-top1" 31*4882a593Smuzhiyun - "samsung,exynos7-clock-ccore" 32*4882a593Smuzhiyun - "samsung,exynos7-clock-peric0" 33*4882a593Smuzhiyun - "samsung,exynos7-clock-peric1" 34*4882a593Smuzhiyun - "samsung,exynos7-clock-peris" 35*4882a593Smuzhiyun - "samsung,exynos7-clock-fsys0" 36*4882a593Smuzhiyun - "samsung,exynos7-clock-fsys1" 37*4882a593Smuzhiyun - "samsung,exynos7-clock-mscl" 38*4882a593Smuzhiyun - "samsung,exynos7-clock-aud" 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun - reg: physical base address of the controller and the length of 41*4882a593Smuzhiyun memory mapped region. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun - #clock-cells: should be 1. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun - clocks: list of clock identifiers which are fed as the input to 46*4882a593Smuzhiyun the given clock controller. Please refer the next section to 47*4882a593Smuzhiyun find the input clocks for a given controller. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun- clock-names: list of names of clocks which are fed as the input 50*4882a593Smuzhiyun to the given clock controller. 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunInput clocks for top0 clock controller: 53*4882a593Smuzhiyun - fin_pll 54*4882a593Smuzhiyun - dout_sclk_bus0_pll 55*4882a593Smuzhiyun - dout_sclk_bus1_pll 56*4882a593Smuzhiyun - dout_sclk_cc_pll 57*4882a593Smuzhiyun - dout_sclk_mfc_pll 58*4882a593Smuzhiyun - dout_sclk_aud_pll 59*4882a593Smuzhiyun 60*4882a593SmuzhiyunInput clocks for top1 clock controller: 61*4882a593Smuzhiyun - fin_pll 62*4882a593Smuzhiyun - dout_sclk_bus0_pll 63*4882a593Smuzhiyun - dout_sclk_bus1_pll 64*4882a593Smuzhiyun - dout_sclk_cc_pll 65*4882a593Smuzhiyun - dout_sclk_mfc_pll 66*4882a593Smuzhiyun 67*4882a593SmuzhiyunInput clocks for ccore clock controller: 68*4882a593Smuzhiyun - fin_pll 69*4882a593Smuzhiyun - dout_aclk_ccore_133 70*4882a593Smuzhiyun 71*4882a593SmuzhiyunInput clocks for peric0 clock controller: 72*4882a593Smuzhiyun - fin_pll 73*4882a593Smuzhiyun - dout_aclk_peric0_66 74*4882a593Smuzhiyun - sclk_uart0 75*4882a593Smuzhiyun 76*4882a593SmuzhiyunInput clocks for peric1 clock controller: 77*4882a593Smuzhiyun - fin_pll 78*4882a593Smuzhiyun - dout_aclk_peric1_66 79*4882a593Smuzhiyun - sclk_uart1 80*4882a593Smuzhiyun - sclk_uart2 81*4882a593Smuzhiyun - sclk_uart3 82*4882a593Smuzhiyun - sclk_spi0 83*4882a593Smuzhiyun - sclk_spi1 84*4882a593Smuzhiyun - sclk_spi2 85*4882a593Smuzhiyun - sclk_spi3 86*4882a593Smuzhiyun - sclk_spi4 87*4882a593Smuzhiyun - sclk_i2s1 88*4882a593Smuzhiyun - sclk_pcm1 89*4882a593Smuzhiyun - sclk_spdif 90*4882a593Smuzhiyun 91*4882a593SmuzhiyunInput clocks for peris clock controller: 92*4882a593Smuzhiyun - fin_pll 93*4882a593Smuzhiyun - dout_aclk_peris_66 94*4882a593Smuzhiyun 95*4882a593SmuzhiyunInput clocks for fsys0 clock controller: 96*4882a593Smuzhiyun - fin_pll 97*4882a593Smuzhiyun - dout_aclk_fsys0_200 98*4882a593Smuzhiyun - dout_sclk_mmc2 99*4882a593Smuzhiyun 100*4882a593SmuzhiyunInput clocks for fsys1 clock controller: 101*4882a593Smuzhiyun - fin_pll 102*4882a593Smuzhiyun - dout_aclk_fsys1_200 103*4882a593Smuzhiyun - dout_sclk_mmc0 104*4882a593Smuzhiyun - dout_sclk_mmc1 105*4882a593Smuzhiyun 106*4882a593SmuzhiyunInput clocks for aud clock controller: 107*4882a593Smuzhiyun - fin_pll 108*4882a593Smuzhiyun - fout_aud_pll 109