1*4882a593SmuzhiyunPLL divider based Dove clocks 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunMarvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide 4*4882a593Smuzhiyunhigh speed clocks for a number of peripherals. These dividers are part of 5*4882a593Smuzhiyunthe PMU, and thus this node should be a child of the PMU node. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThe following clocks are provided: 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunID Clock 10*4882a593Smuzhiyun------------- 11*4882a593Smuzhiyun0 AXI bus clock 12*4882a593Smuzhiyun1 GPU clock 13*4882a593Smuzhiyun2 VMeta clock 14*4882a593Smuzhiyun3 LCD clock 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRequired properties: 17*4882a593Smuzhiyun- compatible : shall be "marvell,dove-divider-clock" 18*4882a593Smuzhiyun- reg : shall be the register address of the Core PLL and Clock Divider 19*4882a593Smuzhiyun Control 0 register. This will cover that register, as well as the 20*4882a593Smuzhiyun Core PLL and Clock Divider Control 1 register. Thus, it will have 21*4882a593Smuzhiyun a size of 8. 22*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyundivider_clk: core-clock@64 { 25*4882a593Smuzhiyun compatible = "marvell,dove-divider-clock"; 26*4882a593Smuzhiyun reg = <0x0064 0x8>; 27*4882a593Smuzhiyun #clock-cells = <1>; 28*4882a593Smuzhiyun}; 29