1*4882a593Smuzhiyun* Clock and reset bindings for CSR atlas7 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "sirf,atlas7-car" 5*4882a593Smuzhiyun- reg: Address and length of the register set 6*4882a593Smuzhiyun- #clock-cells: Should be <1> 7*4882a593Smuzhiyun- #reset-cells: Should be <1> 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe clock consumer should specify the desired clock by having the clock 10*4882a593SmuzhiyunID in its "clocks" phandle cell. 11*4882a593SmuzhiyunThe ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunThe reset consumer should specify the desired reset by having the reset 14*4882a593SmuzhiyunID in its "reset" phandle cell. 15*4882a593SmuzhiyunThe ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExamples: Clock and reset controller node: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyuncar: clock-controller@18620000 { 20*4882a593Smuzhiyun compatible = "sirf,atlas7-car"; 21*4882a593Smuzhiyun reg = <0x18620000 0x1000>; 22*4882a593Smuzhiyun #clock-cells = <1>; 23*4882a593Smuzhiyun #reset-cells = <1>; 24*4882a593Smuzhiyun}; 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExamples: Consumers using clock or reset: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyuntimer@10dc0000 { 29*4882a593Smuzhiyun compatible = "sirf,macro-tick"; 30*4882a593Smuzhiyun reg = <0x10dc0000 0x1000>; 31*4882a593Smuzhiyun clocks = <&car 54>; 32*4882a593Smuzhiyun interrupts = <0 0 0>, 33*4882a593Smuzhiyun <0 1 0>, 34*4882a593Smuzhiyun <0 2 0>, 35*4882a593Smuzhiyun <0 49 0>, 36*4882a593Smuzhiyun <0 50 0>, 37*4882a593Smuzhiyun <0 51 0>; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunuart1: uart@18020000 { 41*4882a593Smuzhiyun cell-index = <1>; 42*4882a593Smuzhiyun compatible = "sirf,macro-uart"; 43*4882a593Smuzhiyun reg = <0x18020000 0x1000>; 44*4882a593Smuzhiyun clocks = <&clks 95>; 45*4882a593Smuzhiyun interrupts = <0 18 0>; 46*4882a593Smuzhiyun fifosize = <32>; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunvpp@13110000 { 50*4882a593Smuzhiyun compatible = "sirf,prima2-vpp"; 51*4882a593Smuzhiyun reg = <0x13110000 0x10000>; 52*4882a593Smuzhiyun interrupts = <0 31 0>; 53*4882a593Smuzhiyun clocks = <&car 85>; 54*4882a593Smuzhiyun resets = <&car 29>; 55*4882a593Smuzhiyun}; 56