1*4882a593Smuzhiyun* Samsung Audio Subsystem Clock Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Samsung Audio Subsystem clock controller generates and supplies clocks 4*4882a593Smuzhiyunto Audio Subsystem block available in the S5PV210 and compatible SoCs. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: should be "samsung,s5pv210-audss-clock". 9*4882a593Smuzhiyun- reg: physical base address and length of the controller's register set. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- #clock-cells: should be 1. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- clocks: 14*4882a593Smuzhiyun - hclk: AHB bus clock of the Audio Subsystem. 15*4882a593Smuzhiyun - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If 16*4882a593Smuzhiyun not specified (i.e. xusbxti is used for PLL reference), it is fixed to 17*4882a593Smuzhiyun a clock named "xxti". 18*4882a593Smuzhiyun - fout_epll: Input PLL to the AudioSS block, parent of mout_audss. 19*4882a593Smuzhiyun - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not 20*4882a593Smuzhiyun specified, it is fixed to a clock named "iiscdclk0". 21*4882a593Smuzhiyun - sclk_audio0: Audio bus clock, parent of mout_i2s. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- clock-names: Aliases for the above clocks. They should be "hclk", 24*4882a593Smuzhiyun "xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunAll available clocks are defined as preprocessor macros in 27*4882a593Smuzhiyundt-bindings/clock/s5pv210-audss-clk.h header and can be used in device 28*4882a593Smuzhiyuntree sources. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExample: Clock controller node. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clk_audss: clock-controller@c0900000 { 33*4882a593Smuzhiyun compatible = "samsung,s5pv210-audss-clock"; 34*4882a593Smuzhiyun reg = <0xc0900000 0x1000>; 35*4882a593Smuzhiyun #clock-cells = <1>; 36*4882a593Smuzhiyun clock-names = "hclk", "xxti", 37*4882a593Smuzhiyun "fout_epll", "sclk_audio0"; 38*4882a593Smuzhiyun clocks = <&clocks DOUT_HCLKP>, <&xxti>, 39*4882a593Smuzhiyun <&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunExample: I2S controller node that consumes the clock generated by the clock 43*4882a593Smuzhiyun controller. Refer to the standard clock bindings for information 44*4882a593Smuzhiyun about 'clocks' and 'clock-names' property. 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun i2s0: i2s@3830000 { 47*4882a593Smuzhiyun /* ... */ 48*4882a593Smuzhiyun clock-names = "iis", "i2s_opclk0", 49*4882a593Smuzhiyun "i2s_opclk1"; 50*4882a593Smuzhiyun clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>, 51*4882a593Smuzhiyun <&clk_audss CLK_DOUT_AUD_BUS>; 52*4882a593Smuzhiyun /* ... */ 53*4882a593Smuzhiyun }; 54