1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/calxeda.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Device Tree Clock bindings for Calxeda highbank platform 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun This binding covers the Calxeda SoC internal peripheral and bus clocks 11*4882a593Smuzhiyun as used by peripherals. The clocks live inside the "system register" 12*4882a593Smuzhiyun region of the SoC, so are typically presented as children of an 13*4882a593Smuzhiyun "hb-sregs" node. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunmaintainers: 16*4882a593Smuzhiyun - Andre Przywara <andre.przywara@arm.com> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunproperties: 19*4882a593Smuzhiyun "#clock-cells": 20*4882a593Smuzhiyun const: 0 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun compatible: 23*4882a593Smuzhiyun enum: 24*4882a593Smuzhiyun - calxeda,hb-pll-clock 25*4882a593Smuzhiyun - calxeda,hb-a9periph-clock 26*4882a593Smuzhiyun - calxeda,hb-a9bus-clock 27*4882a593Smuzhiyun - calxeda,hb-emmc-clock 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun reg: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clocks: 33*4882a593Smuzhiyun maxItems: 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunrequired: 36*4882a593Smuzhiyun - "#clock-cells" 37*4882a593Smuzhiyun - compatible 38*4882a593Smuzhiyun - clocks 39*4882a593Smuzhiyun - reg 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunadditionalProperties: false 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunexamples: 44*4882a593Smuzhiyun - | 45*4882a593Smuzhiyun sregs@3fffc000 { 46*4882a593Smuzhiyun compatible = "calxeda,hb-sregs"; 47*4882a593Smuzhiyun reg = <0x3fffc000 0x1000>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun clocks { 50*4882a593Smuzhiyun #address-cells = <1>; 51*4882a593Smuzhiyun #size-cells = <0>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun osc: oscillator { 54*4882a593Smuzhiyun #clock-cells = <0>; 55*4882a593Smuzhiyun compatible = "fixed-clock"; 56*4882a593Smuzhiyun clock-frequency = <33333000>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun ddrpll: ddrpll@108 { 60*4882a593Smuzhiyun #clock-cells = <0>; 61*4882a593Smuzhiyun compatible = "calxeda,hb-pll-clock"; 62*4882a593Smuzhiyun clocks = <&osc>; 63*4882a593Smuzhiyun reg = <0x108>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun a9pll: a9pll@100 { 67*4882a593Smuzhiyun #clock-cells = <0>; 68*4882a593Smuzhiyun compatible = "calxeda,hb-pll-clock"; 69*4882a593Smuzhiyun clocks = <&osc>; 70*4882a593Smuzhiyun reg = <0x100>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun a9periphclk: a9periphclk@104 { 74*4882a593Smuzhiyun #clock-cells = <0>; 75*4882a593Smuzhiyun compatible = "calxeda,hb-a9periph-clock"; 76*4882a593Smuzhiyun clocks = <&a9pll>; 77*4882a593Smuzhiyun reg = <0x104>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun... 83