1*4882a593SmuzhiyunBroadcom BCM2835 CPRMAN clocks 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding: 4*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/clock-bindings.txt 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe CPRMAN clock controller generates clocks in the audio power domain 7*4882a593Smuzhiyunof the BCM2835. There is a level of PLLs deriving from an external 8*4882a593Smuzhiyunoscillator, a level of PLL dividers that produce channels off of the 9*4882a593Smuzhiyunfew PLLs, and a level of mostly-generic clock generators sourcing from 10*4882a593Smuzhiyunthe PLL channels. Most other hardware components source from the 11*4882a593Smuzhiyunclock generators, but a few (like the ARM or HDMI) will source from 12*4882a593Smuzhiyunthe PLL dividers directly. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired properties: 15*4882a593Smuzhiyun- compatible: should be one of the following, 16*4882a593Smuzhiyun "brcm,bcm2711-cprman" 17*4882a593Smuzhiyun "brcm,bcm2835-cprman" 18*4882a593Smuzhiyun- #clock-cells: Should be <1>. The permitted clock-specifier values can be 19*4882a593Smuzhiyun found in include/dt-bindings/clock/bcm2835.h 20*4882a593Smuzhiyun- reg: Specifies base physical address and size of the registers 21*4882a593Smuzhiyun- clocks: phandles to the parent clocks used as input to the module, in 22*4882a593Smuzhiyun the following order: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun - External oscillator 25*4882a593Smuzhiyun - DSI0 byte clock 26*4882a593Smuzhiyun - DSI0 DDR2 clock 27*4882a593Smuzhiyun - DSI0 DDR clock 28*4882a593Smuzhiyun - DSI1 byte clock 29*4882a593Smuzhiyun - DSI1 DDR2 clock 30*4882a593Smuzhiyun - DSI1 DDR clock 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun Only external oscillator is required. The DSI clocks may 33*4882a593Smuzhiyun not be present, in which case their children will be 34*4882a593Smuzhiyun unusable. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunExample: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clk_osc: clock@3 { 39*4882a593Smuzhiyun compatible = "fixed-clock"; 40*4882a593Smuzhiyun reg = <3>; 41*4882a593Smuzhiyun #clock-cells = <0>; 42*4882a593Smuzhiyun clock-output-names = "osc"; 43*4882a593Smuzhiyun clock-frequency = <19200000>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun clocks: cprman@7e101000 { 47*4882a593Smuzhiyun compatible = "brcm,bcm2835-cprman"; 48*4882a593Smuzhiyun #clock-cells = <1>; 49*4882a593Smuzhiyun reg = <0x7e101000 0x2000>; 50*4882a593Smuzhiyun clocks = <&clk_osc>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun i2c0: i2c@7e205000 { 54*4882a593Smuzhiyun compatible = "brcm,bcm2835-i2c"; 55*4882a593Smuzhiyun reg = <0x7e205000 0x1000>; 56*4882a593Smuzhiyun interrupts = <2 21>; 57*4882a593Smuzhiyun clocks = <&clocks BCM2835_CLOCK_VPU>; 58*4882a593Smuzhiyun #address-cells = <1>; 59*4882a593Smuzhiyun #size-cells = <0>; 60*4882a593Smuzhiyun }; 61