1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/bitmain,bm1880-clk.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Bitmain BM1880 Clock Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The Bitmain BM1880 clock controller generates and supplies clock to 14*4882a593Smuzhiyun various peripherals within the SoC. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun This binding uses common clock bindings 17*4882a593Smuzhiyun [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunproperties: 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun const: bitmain,bm1880-clk 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg: 24*4882a593Smuzhiyun items: 25*4882a593Smuzhiyun - description: pll registers 26*4882a593Smuzhiyun - description: system registers 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun reg-names: 29*4882a593Smuzhiyun items: 30*4882a593Smuzhiyun - const: pll 31*4882a593Smuzhiyun - const: sys 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clock-names: 37*4882a593Smuzhiyun const: osc 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun '#clock-cells': 40*4882a593Smuzhiyun const: 1 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunrequired: 43*4882a593Smuzhiyun - compatible 44*4882a593Smuzhiyun - reg 45*4882a593Smuzhiyun - reg-names 46*4882a593Smuzhiyun - clocks 47*4882a593Smuzhiyun - clock-names 48*4882a593Smuzhiyun - '#clock-cells' 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunadditionalProperties: false 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunexamples: 53*4882a593Smuzhiyun # Clock controller node: 54*4882a593Smuzhiyun - | 55*4882a593Smuzhiyun clk: clock-controller@e8 { 56*4882a593Smuzhiyun compatible = "bitmain,bm1880-clk"; 57*4882a593Smuzhiyun reg = <0xe8 0x0c>, <0x800 0xb0>; 58*4882a593Smuzhiyun reg-names = "pll", "sys"; 59*4882a593Smuzhiyun clocks = <&osc>; 60*4882a593Smuzhiyun clock-names = "osc"; 61*4882a593Smuzhiyun #clock-cells = <1>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun # Example UART controller node that consumes clock generated by the clock controller: 65*4882a593Smuzhiyun - | 66*4882a593Smuzhiyun uart0: serial@58018000 { 67*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 68*4882a593Smuzhiyun reg = <0x58018000 0x2000>; 69*4882a593Smuzhiyun clocks = <&clk 45>, <&clk 46>; 70*4882a593Smuzhiyun clock-names = "baudclk", "apb_pclk"; 71*4882a593Smuzhiyun interrupts = <0 9 4>; 72*4882a593Smuzhiyun reg-shift = <2>; 73*4882a593Smuzhiyun reg-io-width = <4>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun... 77