1*4882a593SmuzhiyunBinding for the AXS10X I2S PLL clock 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: shall be "snps,axs10x-i2s-pll-clock" 9*4882a593Smuzhiyun- reg : address and length of the I2S PLL register set. 10*4882a593Smuzhiyun- clocks: shall be the input parent clock phandle for the PLL. 11*4882a593Smuzhiyun- #clock-cells: from common clock binding; Should always be set to 0. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample: 14*4882a593Smuzhiyun pll_clock: pll_clock { 15*4882a593Smuzhiyun compatible = "fixed-clock"; 16*4882a593Smuzhiyun clock-frequency = <27000000>; 17*4882a593Smuzhiyun #clock-cells = <0>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun i2s_clock@100a0 { 21*4882a593Smuzhiyun compatible = "snps,axs10x-i2s-pll-clock"; 22*4882a593Smuzhiyun reg = <0x100a0 0x10>; 23*4882a593Smuzhiyun clocks = <&pll_clock>; 24*4882a593Smuzhiyun #clock-cells = <0>; 25*4882a593Smuzhiyun }; 26