1*4882a593SmuzhiyunBinding for the axi-clkgen clock generator 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a". 9*4882a593Smuzhiyun- #clock-cells : from common clock binding; Should always be set to 0. 10*4882a593Smuzhiyun- reg : Address and length of the axi-clkgen register set. 11*4882a593Smuzhiyun- clocks : Phandle and clock specifier for the parent clock(s). This must 12*4882a593Smuzhiyun either reference one clock if only the first clock input is connected or two 13*4882a593Smuzhiyun if both clock inputs are connected. For the later case the clock connected 14*4882a593Smuzhiyun to the first input must be specified first. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional properties: 17*4882a593Smuzhiyun- clock-output-names : From common clock binding. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyun clock@ff000000 { 21*4882a593Smuzhiyun compatible = "adi,axi-clkgen"; 22*4882a593Smuzhiyun #clock-cells = <0>; 23*4882a593Smuzhiyun reg = <0xff000000 0x1000>; 24*4882a593Smuzhiyun clocks = <&osc 1>; 25*4882a593Smuzhiyun }; 26