1*4882a593SmuzhiyunDevice Tree Clock bindings for arch-at91 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunSlow Clock controller: 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun- compatible : shall be one of the following: 11*4882a593Smuzhiyun "atmel,at91sam9x5-sckc", 12*4882a593Smuzhiyun "atmel,sama5d3-sckc", 13*4882a593Smuzhiyun "atmel,sama5d4-sckc" or 14*4882a593Smuzhiyun "microchip,sam9x60-sckc": 15*4882a593Smuzhiyun at91 SCKC (Slow Clock Controller) 16*4882a593Smuzhiyun- #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0. 17*4882a593Smuzhiyun- clocks : shall be the input parent clock phandle for the clock. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional properties: 20*4882a593Smuzhiyun- atmel,osc-bypass : boolean property. Set this when a clock signal is directly 21*4882a593Smuzhiyun provided on XIN. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunFor example: 24*4882a593Smuzhiyun sckc@fffffe50 { 25*4882a593Smuzhiyun compatible = "atmel,at91sam9x5-sckc"; 26*4882a593Smuzhiyun reg = <0xfffffe50 0x4>; 27*4882a593Smuzhiyun clocks = <&slow_xtal>; 28*4882a593Smuzhiyun #clock-cells = <0>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunPower Management Controller (PMC): 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunRequired properties: 34*4882a593Smuzhiyun- compatible : shall be "atmel,<chip>-pmc", "syscon" or 35*4882a593Smuzhiyun "microchip,sam9x60-pmc" 36*4882a593Smuzhiyun <chip> can be: at91rm9200, at91sam9260, at91sam9261, 37*4882a593Smuzhiyun at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15, 38*4882a593Smuzhiyun at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5, 39*4882a593Smuzhiyun sama5d2, sama5d3 or sama5d4. 40*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 2. The first entry 41*4882a593Smuzhiyun is the type of the clock (core, system, peripheral or generated) and the 42*4882a593Smuzhiyun second entry its index as provided by the datasheet 43*4882a593Smuzhiyun- clocks : Must contain an entry for each entry in clock-names. 44*4882a593Smuzhiyun- clock-names: Must include the following entries: "slow_clk", "main_xtal" 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunOptional properties: 47*4882a593Smuzhiyun- atmel,osc-bypass : boolean property. Set this when a clock signal is directly 48*4882a593Smuzhiyun provided on XIN. 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunFor example: 51*4882a593Smuzhiyun pmc: pmc@f0018000 { 52*4882a593Smuzhiyun compatible = "atmel,sama5d4-pmc", "syscon"; 53*4882a593Smuzhiyun reg = <0xf0018000 0x120>; 54*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 55*4882a593Smuzhiyun #clock-cells = <2>; 56*4882a593Smuzhiyun clocks = <&clk32k>, <&main_xtal>; 57*4882a593Smuzhiyun clock-names = "slow_clk", "main_xtal"; 58*4882a593Smuzhiyun }; 59