1*4882a593Smuzhiyun* Amlogic GXBB AO Clock and Reset Unit 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Amlogic GXBB AO clock controller generates and supplies clock to various 4*4882a593Smuzhiyuncontrollers within the Always-On part of the SoC. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: value should be different for each SoC family as : 9*4882a593Smuzhiyun - GXBB (S905) : "amlogic,meson-gxbb-aoclkc" 10*4882a593Smuzhiyun - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" 11*4882a593Smuzhiyun - GXM (S912) : "amlogic,meson-gxm-aoclkc" 12*4882a593Smuzhiyun - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" 13*4882a593Smuzhiyun - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc" 14*4882a593Smuzhiyun followed by the common "amlogic,meson-gx-aoclkc" 15*4882a593Smuzhiyun- clocks: list of clock phandle, one for each entry clock-names. 16*4882a593Smuzhiyun- clock-names: should contain the following: 17*4882a593Smuzhiyun * "xtal" : the platform xtal 18*4882a593Smuzhiyun * "mpeg-clk" : the main clock controller mother clock (aka clk81) 19*4882a593Smuzhiyun * "ext-32k-0" : external 32kHz reference #0 if any (optional) 20*4882a593Smuzhiyun * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only) 21*4882a593Smuzhiyun * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- #clock-cells: should be 1. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes can use this identifier 26*4882a593Smuzhiyunto specify the clock which they consume. All available clocks are defined as 27*4882a593Smuzhiyunpreprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be 28*4882a593Smuzhiyunused in device tree sources. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun- #reset-cells: should be 1. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunEach reset is assigned an identifier and client nodes can use this identifier 33*4882a593Smuzhiyunto specify the reset which they consume. All available resets are defined as 34*4882a593Smuzhiyunpreprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be 35*4882a593Smuzhiyunused in device tree sources. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunParent node should have the following properties : 38*4882a593Smuzhiyun- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" 39*4882a593Smuzhiyun- reg: base address and size of the AO system control register space. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunExample: AO Clock controller node: 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunao_sysctrl: sys-ctrl@0 { 44*4882a593Smuzhiyun compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; 45*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x100>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun clkc_AO: clock-controller { 48*4882a593Smuzhiyun compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; 49*4882a593Smuzhiyun #clock-cells = <1>; 50*4882a593Smuzhiyun #reset-cells = <1>; 51*4882a593Smuzhiyun clocks = <&xtal>, <&clkc CLKID_CLK81>; 52*4882a593Smuzhiyun clock-names = "xtal", "mpeg-clk"; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunExample: UART controller node that consumes the clock and reset generated 56*4882a593Smuzhiyun by the clock controller: 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun uart_AO: serial@4c0 { 59*4882a593Smuzhiyun compatible = "amlogic,meson-uart"; 60*4882a593Smuzhiyun reg = <0x4c0 0x14>; 61*4882a593Smuzhiyun interrupts = <0 90 1>; 62*4882a593Smuzhiyun clocks = <&clkc_AO CLKID_AO_UART1>; 63*4882a593Smuzhiyun resets = <&clkc_AO RESET_AO_UART1>; 64*4882a593Smuzhiyun }; 65