1*4882a593Smuzhiyun* Amlogic AXG Audio Clock Controllers 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Amlogic AXG audio clock controller generates and supplies clock to the 4*4882a593Smuzhiyunother elements of the audio subsystem, such as fifos, i2s, spdif and pdm 5*4882a593Smuzhiyundevices. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired Properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D, 10*4882a593Smuzhiyun "amlogic,g12a-audio-clkc" for G12A, 11*4882a593Smuzhiyun "amlogic,sm1-audio-clkc" for S905X3. 12*4882a593Smuzhiyun- reg : physical base address of the clock controller and length of 13*4882a593Smuzhiyun memory mapped region. 14*4882a593Smuzhiyun- clocks : a list of phandle + clock-specifier pairs for the clocks listed 15*4882a593Smuzhiyun in clock-names. 16*4882a593Smuzhiyun- clock-names : must contain the following: 17*4882a593Smuzhiyun * "pclk" - Main peripheral bus clock 18*4882a593Smuzhiyun may contain the following: 19*4882a593Smuzhiyun * "mst_in[0-7]" - 8 input plls to generate clock signals 20*4882a593Smuzhiyun * "slv_sclk[0-9]" - 10 slave bit clocks provided by external 21*4882a593Smuzhiyun components. 22*4882a593Smuzhiyun * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external 23*4882a593Smuzhiyun components. 24*4882a593Smuzhiyun- resets : phandle of the internal reset line 25*4882a593Smuzhiyun- #clock-cells : should be 1. 26*4882a593Smuzhiyun- #reset-cells : should be 1 on the g12a (and following) soc family 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes can use this identifier 29*4882a593Smuzhiyunto specify the clock which they consume. All available clocks are defined as 30*4882a593Smuzhiyunpreprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be 31*4882a593Smuzhiyunused in device tree sources. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunExample: 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunclkc_audio: clock-controller@0 { 36*4882a593Smuzhiyun compatible = "amlogic,axg-audio-clkc"; 37*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0xb4>; 38*4882a593Smuzhiyun #clock-cells = <1>; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun clocks = <&clkc CLKID_AUDIO>, 41*4882a593Smuzhiyun <&clkc CLKID_MPLL0>, 42*4882a593Smuzhiyun <&clkc CLKID_MPLL1>, 43*4882a593Smuzhiyun <&clkc CLKID_MPLL2>, 44*4882a593Smuzhiyun <&clkc CLKID_MPLL3>, 45*4882a593Smuzhiyun <&clkc CLKID_HIFI_PLL>, 46*4882a593Smuzhiyun <&clkc CLKID_FCLK_DIV3>, 47*4882a593Smuzhiyun <&clkc CLKID_FCLK_DIV4>, 48*4882a593Smuzhiyun <&clkc CLKID_GP0_PLL>; 49*4882a593Smuzhiyun clock-names = "pclk", 50*4882a593Smuzhiyun "mst_in0", 51*4882a593Smuzhiyun "mst_in1", 52*4882a593Smuzhiyun "mst_in2", 53*4882a593Smuzhiyun "mst_in3", 54*4882a593Smuzhiyun "mst_in4", 55*4882a593Smuzhiyun "mst_in5", 56*4882a593Smuzhiyun "mst_in6", 57*4882a593Smuzhiyun "mst_in7"; 58*4882a593Smuzhiyun resets = <&reset RESET_AUDIO>; 59*4882a593Smuzhiyun}; 60